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    EVLSTGAP3S3S

    Half-bridge evaluation board for STGAP3S3S SiC MOSFET galvanically isolated gate driver with protection

    Parameters
    ECCN USEAR99
    ECCN EUNEC
    Packing TypeNot Applicable
    RoHs compliantEcopack1
    GradeIndustrial
    Package NameCARD
    Description

    The EVLSTGAP3S3S is a half-bridge evaluation board designed to evaluate the STGAP3S3S isolated single gate driver.The STGAP3S3S is characterized by 3 A current capability, rail-to-rail outputs, and optimized UVLO and DESAT protection thresholds for SiC MOSFETs, which makes the device optimal for...
    Read More

    Key features
    Key features
    • Board
      • Half-bridge configuration
      • High-voltage rail up to 1200 V (limited by the SiC MOSFET’s
        and capacitor’s rating)
      • SCT10N120AG SiCs: 1200 V, 12 A
      • Compatible with 5 V and 3.3 V MCUs
      • VDD logic supplied by onboard-generated 3.3 V or VAUX = 5 V
      • Onboard isolated DC-DC converters to supply high-side and
        low-side gate drivers, fed by VAUX = 5 V, with 5.4 kVpk maximum isolation
      • Easy jumper selection of driving voltage configuration:+15/0 V; +15/-4.7 V; +12/0 V; +12/-4.7
        V
      • Fault LED indicators
      • Maximum working voltage across isolation: 1200 V
      • RoHS compliant
    • STGAP3S3S device
      • Driver current capability: 3 A
        source/sink @ 25 °C
      • 75 ns input-output propagation delay
      • Internal Miller CLAMP
      • UVLO function
      • Desaturation protection
      • Adjustable soft turn-off
      • Gate driving voltage up to 32 V
      • Negative gate driving voltage
      • 3.3 V, 5 V TTL/CMOS inputs with
        hysteresis
      • Temperature shutdown protection
      • Reinforced galvanic isolation:Isolation voltage VISO = 5.7 kVRMS (UL 1577)Transient overvoltage VIOTM = 8 kVPEAK (IEC 60747-17)Max. repetitive isolation voltage VIORM = 1.2 kVPEAK (IEC 60747-17)
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    Parameters
    ECCN USEAR99
    ECCN EUNEC
    Packing TypeNot Applicable
    RoHs compliantEcopack1
    GradeIndustrial
    Package NameCARD
    Description

    The EVLSTGAP3S3S is a half-bridge evaluation board designed to evaluate the STGAP3S3S isolated single gate driver.The STGAP3S3S is characterized by 3 A current capability, rail-to-rail outputs, and optimized UVLO and DESAT protection thresholds for SiC MOSFETs, which makes the device optimal for...
    Read More

    Key features
    Key features
    • Board
      • Half-bridge configuration
      • High-voltage rail up to 1200 V (limited by the SiC MOSFET’s
        and capacitor’s rating)
      • SCT10N120AG SiCs: 1200 V, 12 A
      • Compatible with 5 V and 3.3 V MCUs
      • VDD logic supplied by onboard-generated 3.3 V or VAUX = 5 V
      • Onboard isolated DC-DC converters to supply high-side and
        low-side gate drivers, fed by VAUX = 5 V, with 5.4 kVpk maximum isolation
      • Easy jumper selection of driving voltage configuration:+15/0 V; +15/-4.7 V; +12/0 V; +12/-4.7
        V
      • Fault LED indicators
      • Maximum working voltage across isolation: 1200 V
      • RoHS compliant
    • STGAP3S3S device
      • Driver current capability: 3 A
        source/sink @ 25 °C
      • 75 ns input-output propagation delay
      • Internal Miller CLAMP
      • UVLO function
      • Desaturation protection
      • Adjustable soft turn-off
      • Gate driving voltage up to 32 V
      • Negative gate driving voltage
      • 3.3 V, 5 V TTL/CMOS inputs with
        hysteresis
      • Temperature shutdown protection
      • Reinforced galvanic isolation:Isolation voltage VISO = 5.7 kVRMS (UL 1577)Transient overvoltage VIOTM = 8 kVPEAK (IEC 60747-17)Max. repetitive isolation voltage VIORM = 1.2 kVPEAK (IEC 60747-17)