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The M95128-DRE is a 128-Kbit serial EEPROM device operating up to 105 °C. The M95128-DRE is compliant with the level of reliability defined by the AEC-Q100 grade 2.
The device is accessed by a simple serial SPI compatible interface running up to 20 MHz.
The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M95128-DRE is a byte-alterable memory (16384 × 8 bits) organized as 256 pages of 64 bytes in which the data integrity is significantly improved with an embedded Error Correction Code logic.
The M95128-DRE offers an additional Identification Page (64 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode.