SPC560P34L1CEFAR

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32-bit Power Architecture MCU for Automotive Chassis and Safety Applications
Learn More about SPC560P34L1CEFAR

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Parameter

Parameter Name	Parameter Value
Supply Voltage Min Volt	3.0
Supply Voltage Max Volt	5.5
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	125.0
Core	e200z0
ECCN US	5A991.b.4.a
ECCN EU	NEC
Packing Type	Tape And Reel
ROHS Compliance Grade	Ecopack2
Grade	Automotive
Package Name	LQFP 64 10x10x1.4 mm

Description

This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest achievement in integrated automotive application controllers. It belongs to an expanding range of automotive-focused products designed to address chassis applications—specifically, electrical hydraulic power steering (EHPS) and electric power steering (EPS)—as well as airbag applications.

This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology.

The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations.

Key features

Key features
Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h) Compliant with Power Architecture^®embedded category Variable Length Encoding (VLE) Memory organization Up to 256 KB on-chip code flash memory with ECC and erase/program controller Additional 64 (4 × 16) KB on-chip data flash memory with ECC for EEPROM emulation Up to 20 KB on-chip SRAM with ECC Fail-safe protection Programmable watchdog timer Non-maskable interrupt Fault collection unit Nexus Class 1 interface Interrupts and events 16-channel eDMA controller 16 priority level controller Up to 25 external interrupts PIT implements four 32-bit timers 120 interrupts are routed via INTC 1 general purpose eTimer unit 6 timers each with up/down capabilities 16-bit resolution, cascadable counters Quadrature decode with rotation direction flag Double buffer input capture and output compare GPIO (37 on LQFP64; 64 on LQFP100) individually programmable as I/O or special function Communications interfaces 2 LINFlex channels (1× Master/Slave, 1× Master only) Up to 3 DSPI channels with automatic chip select generation (up to 8/4/4 chip selects) Up to 2 FlexCAN interface (2.0B Active) with 32 message buffers 1 safety port based on FlexCAN with 32 message buffers and up to 8 Mbit/s at 64 MHz capability usable as second CAN when not used as safety port One 10-bit analog-to-digital converter (ADC) Up to 16 input channels (16 on LQFP100 / 12 on LQFP64) Conversion time < 1 μs including sampling time at full precision Programmable Cross Triggering Unit (CTU) 4 analog watchdogs with interrupt capability On-chip CAN/UART bootstrap loader with Boot Assist Module (BAM) 1

SPC560P34L1BEABY

SPC560P34L1CEFAR

Active

32-bit Power Architecture MCU for Automotive Chassis and Safety Applications Learn More about SPC560P34L1CEFAR

32-bit Power Architecture MCU for Automotive Chassis and Safety Applications
Learn More about SPC560P34L1CEFAR