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    SPC560P54L3BEABY

    SPC560P54L3BEABY

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    SPC560P54L3BEABR

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    32-bit Power Architecture MCU for Automotive Chassis and Safety Applications
    Learn More about SPC560P54L3BEABR

    Quantity $ per Unit Savings
    1 - 9$9.990%
    10 - 24$6.8432%
    25 - 99$6.5335%
    100 - 249$5.7143%
    250 - 499$5.5544%
    500$4.7153%
    500 + Contact Sales
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    Parameter NameParameter Value
    Supply Voltage Min Volt3.0
    Supply Voltage Max Volt5.5
    Operating Temp Min Celsius-40.0
    Operating Temp Max Celsius105.0
    Coree200z0
    ECCN US5A991B4A
    ECCN EUNEC
    Packing TypeTape And Reel
    ROHS Compliance GradeEcopack2
    GradeAutomotive
    Package NameLQFP 100 14x14x1.4 mm
    Key features
    • 64 MHz, single issue, 32-bit CPU core complex (e200z0h)
      • Compliant with Power Architecture®embedded category
      • Variable Length Encoding (VLE)
    • Memory organizazion
      • Up to 1024 KB on-chip code Flash memory with additional 64 KB for EEPROM emulation (data flash), with ECC, with erase/program controller
      • Up to 80 KB on-chip SRAM with ECC
    • Fail safe protection
      • ECC protection on system SRAM and Flash
      • Safety port
      • SWT with servicing sequence pseudo-random generator
      • Power management
      • Non-maskable interrupt for both cores
      • Fault collection and control unit (FCCU)
      • Safe mode of system-on-chip (SoC)
      • Register protection scheme
    • Nexus®L2+ interface
    • Single 3.3 V or 5 V supply for I/Os and ADC
    • 2 on-platform peripherals set with 2 INTC
    • 16-channel eDMA controller with multiple transfer request sources
    • General purpose I/Os (80 GPIO + 26 GPI on LQFP144; 49 GPIO + 16 GPI on LQFP100)
    • 2 general purpose eTimer units
      • 6 timers, each with up/down count capabilities
      • 16-bit resolution, cascadable counters
      • Quadrature decode with rotation direction flag
      • Double buffer input capture and output compare
    • Communications interfaces
      • 2 LINFlex modules (LIN 2.1, 1 × Master/Slave, 1 × Master Only)
      • 5 DSPI modules with automatic chip select generation
      • 2 FlexCAN interfaces (2.0B Active) with 32 message buffers
      • 1 Safety port based on FlexCAN; usable as third CAN when not used as safety port
      • 1 FlexRay™ module (V2.1) with dual or single channel, 64 message buffers and up to 10 Mbit/s
    • 2 CRC units with three contexts and 3 hardwired polynomials(CRC8,CRC32 and CRC-16-CCITT)
    • 10-bit A/D converter
      • 27 input channels and pre-sampling feature
      • Conversion time < 1 μs including sampling time a
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