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These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices that contain all the features of the SPC563Mxx family and many new features coupled with high performance 90 nm CMOS technology to provide substantial reduction of cost per feature and significant performance improvement.
The advanced and cost-efficient host processor core of this automotive controller family is built on Power Architecture technology. This family contains enhancements that improve the architecture’s fit in embedded applications, includes additional instruction support for digital signal processing (DSP), integrates technologies — such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system — that are important for today’s lower-end powertrain applications.
The device has a single level of memory hierarchy consisting of up to 94 KB on-chip SRAM and up to 1.5 MB of internal flash memory. The device also has an external bus interface (EBI) for ‘calibration’. This external bus interface has been designed to support most of the standard memories used with the SPC564Axx and SPC563Mxx families.
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