SPC564A70L7COBY

SPC564A70L7COBY

SPC564A70L7CFBR

SPC564A70L7CFBR

SPC564A70L7CFAR

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32-bit Power Architecture MCU for Automotive Powertrain Applications

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1 - 499$22.320%
500$15.4131%
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$22.32
Parameter NameParameter Value
Operating RangeAutomotive
Supply Voltage Min Volt4.5
Supply Voltage Max Volt5.5
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius125.0
Coree200z4d
ECCN US5A991B4A
ECCN EUNEC
Packing TypeTape And Reel
ROHS Compliance GradeEcopack2
GradeAutomotive
Package NameLQFP 176 24x24x1.4 mm
Key features
  • 150 MHz e200z4 Power Architecture®core
    • Variable length instruction encoding (VLE)
    • Superscalar architecture with 2 execution units
    • Up to 2 integer or floating point instructions per cycle
    • Up to 4 multiply and accumulate operations per cycle
  • Memory organization
    • 2 MB on-chip flash memory with ECC and read-while-write (RWW)
    • 128 KB on-chip SRAM with standby functionality (32 KB) and ECC
    • 8 KB instruction cache (with line locking), configurable as 2- or 4-way
    • 14 + 3 KB eTPU code and data RAM
    • 4 x 4 crossbar switch (XBAR)
    • 24-entry MMU
  • Fail Safe Protection
    • 16-entry Memory Protection Unit (MPU)
    • CRC unit with 3 submodules
    • Junction temperature sensor
  • Interrupt
    • Configurable interrupt controller (INTC) with non-maskable interrupt (NMI)
    • 64-channel eDMA
  • Serial channels
    • 3 eSCI modules
    • 3 DSPI modules (2 of which support downstream Micro Second Channel [MSC])
    • 3 FlexCAN modules with 64 message buffers each
    • 1 FlexRay module (V2.1) up to 10 Mbit/s w/dual or single channel, 128 message objects, ECC
  • 1 eMIOS (24 unified channels)
  • 1 eTPU2 (second generation eTPU)
    • 32 standard channels
    • 1 reaction module (6 channels with 3 outputs per channel)
  • 2 enhanced queued analog-to-digital converters (eQADCs)
    • Forty 12-bit input channels
    • 688 ns minimum conversion time
  • On-chip CAN/SCI Bootstrap loader with Boot Assist Module (BAM)
  • Nexus: Class 3+ for core; Class 1 for eTPU
  • JTAG (5-pin)
  • Development Trigger Semaphore (DTS)
  • Clock generation
    • On-chip 4-40 MHz main oscillator
    • On-chip FMPLL (frequency-modulated phase-locked loop)
  • Up to 112 general purpose I/O lines
  • Power reduction modes: slow, stop, and standby