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This microcontroller is a 32-bit system-on-chip (SoC) device intended for use in mid-range engine control and automotive transmission control applications.
It is compatible with devices in ST's SPC56xx family and offers performance and capability above that of the SPC563M devices.
The microcontroller's e200z4 host processor core is built on the Power Architecture technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP).
The device has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by a 128 KB on-chip SRAM and a 2 MB internal flash memory.
For development, the device includes a calibration bus that is accessible only when using the STMicroelectronics calibration tool.