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    SPC564A80L7COBR

    SPC564A80L7COBR

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    SPC564A80L7CFAR

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    32-bit Power Architecture MCU for Automotive Powertrain Applications
    Learn More about SPC564A80L7CFAR

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    Parameter NameParameter Value
    Operating RangeAutomotive
    Supply Voltage Min Volt4.5
    Supply Voltage Max Volt5.5
    Operating Temp Min Celsius-40.0
    Operating Temp Max Celsius125.0
    Coree200z4d
    ECCN US5A991.b.4.a
    ECCN EUNEC
    Packing TypeTape And Reel
    RoHs compliantEcopack2
    GradeAutomotive
    Package NameLQFP 176 24x24x1.4 mm

    The microcontroller’s e200z4 host processor core is built on Power Architecture technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP).

    Key features
    • 150 MHz e200z4 Power Architecture core
      • Variable length instruction encoding (VLE)
      • Superscalar architecture with 2 execution units
      • Up to 2 integer or floating point instructions per cycle
      • Up to 4 multiply and accumulate operations per cycle
    • Memory organization
      • 4 MB on-chip flash memory with ECC and Read While Write (RWW)
      • 192 KB on-chip RAM with standby functionality (32 KB) and ECC
      • 8 KB instruction cache (with line locking), configurable as 2- or 4-way
      • 14 + 3 KB eTPU code and data RAM
      • 5 × 4 crossbar switch (XBAR)
      • 24-entry MMU
      • External Bus Interface (EBI) with slave and master port
    • Fail Safe Protection
      • 16-entry Memory Protection Unit (MPU)
      • CRC unit with 3 sub-modules
      • Junction temperature sensor
    • Interrupts
      • Configurable interrupt controller (with NMI)
      • 64-channel DMA
    • Serial channels
      • 3 × eSCI
      • 3 × DSPI (2 of which support downstream Micro Second Channel [MSC])
      • 3 × FlexCAN with 64 messages each
      • 1 × FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC
    • 1 × eMIOS
      • 24 unified channels
    • 1 × eTPU2 (second generation eTPU)
      • 32 standard channels
      • 1 × reaction module (6 channels with three outputs per channel)
    • 2 enhanced queued analog-to-digital converters (eQADCs)
      • Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external multiplexers
      • 6 command queues
      • Trigger and DMA support
      • 688 ns minimum conversion time
    • On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM)
    • Nexus: Class 3+ for core; Class 1 for the eTPU
    • JTAG (5-pin)
    • Development Trigger Semaphore (DTS)
    • Clock generation
      • On-chip 4–40 MHz main oscillato
    Associated Products