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SPC56EL54L5CBFSR

SPC56EL54L5CBFSR

Active

SPC56EL54L5CBFSY

32-bit Power Architecture MCU for Automotive Chassis and Safety Applications

Supply Voltage Min Volt3.0
Supply Voltage Max Volt3.6
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius125.0
CoreDual e200z4d
ECCN US5A991.b.4.a
ECCN EUNEC
Packing TypeTray
RoHs compliantEcopack2
GradeAutomotive Safety
Package NameLQFP 144 20x20x1.4 mm

The Leopard series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital signal processing (DSP) and integrate...
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Key features
  • High-performance e200z4d dual core
  • 32-bit Power Architecture® technology CPU
  • Core frequency as high as 120 MHz
  • Dual issue five-stage pipeline core
  • Variable Length Encoding (VLE)
  • Memory Management Unit (MMU)
  • 4 KB instruction cache with error detection code
  • Signal processing engine (SPE)
  • Memory available
    • 1 MB flash memory with ECC
    • 128 KB on-chip SRAM with ECC
    • Built-in RWW capabilities for EEPROM emulation
  • SIL3/ASILD innovative safety concept: LockStep mode and Fail-safe protection
    • Sphere of replication (SoR) for key components (such as CPU core, eDMA, crossbar switch)
    • Fault collection and control unit (FCCU)
    • Redundancy control and checker unit (RCCU) on outputs of the SoR connected to FCCU
    • Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware
    • Boot-time Built-In Self-Test for ADC and flash memory triggered by software
    • Replicated safety enhanced watchdog
    • Replicated junction temperature sensor
    • Non-maskable interrupt (NMI)
    • 16-region memory protection unit (MPU)
    • Clock monitoring units (CMU)
    • Power management unit (PMU)
    • Cyclic redundancy check (CRC) unit
  • Decoupled Parallel mode for high-performance use of replicated cores
  • Nexus Class 3+ interface
  • Interrupts
    • Replicated 16-priority controller
    • Replicated 16-channel eDMA controller
  • GPIOs individually programmable as input, output or special function
  • Three 6-channel general-purpose eTimer units
  • 2 FlexPWM units
    • Four 16-bit channels per module
  • Communications interfaces
    • 2 LINFlexD channels
    • 3 DSPI channels with automatic chip select generation
    • 2 FlexCAN interfaces (2.0B Active) with 32 message objects
    • FlexRay module (V2.1 Rev. A) with 2 channels, 64 message buffers and data rates up to 10 Mbit/s
  • Two 12-bit analog-to-digital converters (ADCs)
    • 16 input channels
    • Programmable cross triggering unit (CTU) to synchronize ADCs conversion with timer and PWM
  • Sine wave generator (D/A with low pass filter)
  • On-chip CAN/UART bootstrap loader
  • Single 3.0 V to 3.6 V voltage supply
  • Ambient temperature range –40 °C to 125 °C
  • Junction temperature range –40 °C to 150 °C
Out of Stock
Quantity $ per unit Savings
1-9$19.600%
10-24$18.018%
25-99$17.2712%
100-249$15.2222%
250-359$14.4826%
360-500$14.4826%
Contact sales
$19.60
Supply Voltage Min Volt3.0
Supply Voltage Max Volt3.6
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius125.0
CoreDual e200z4d
ECCN US5A991.b.4.a
ECCN EUNEC
Packing TypeTray
RoHs compliantEcopack2
GradeAutomotive Safety
Package NameLQFP 144 20x20x1.4 mm

The Leopard series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital signal processing (DSP) and integrate...
Read More

Key features
  • High-performance e200z4d dual core
  • 32-bit Power Architecture® technology CPU
  • Core frequency as high as 120 MHz
  • Dual issue five-stage pipeline core
  • Variable Length Encoding (VLE)
  • Memory Management Unit (MMU)
  • 4 KB instruction cache with error detection code
  • Signal processing engine (SPE)
  • Memory available
    • 1 MB flash memory with ECC
    • 128 KB on-chip SRAM with ECC
    • Built-in RWW capabilities for EEPROM emulation
  • SIL3/ASILD innovative safety concept: LockStep mode and Fail-safe protection
    • Sphere of replication (SoR) for key components (such as CPU core, eDMA, crossbar switch)
    • Fault collection and control unit (FCCU)
    • Redundancy control and checker unit (RCCU) on outputs of the SoR connected to FCCU
    • Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware
    • Boot-time Built-In Self-Test for ADC and flash memory triggered by software
    • Replicated safety enhanced watchdog
    • Replicated junction temperature sensor
    • Non-maskable interrupt (NMI)
    • 16-region memory protection unit (MPU)
    • Clock monitoring units (CMU)
    • Power management unit (PMU)
    • Cyclic redundancy check (CRC) unit
  • Decoupled Parallel mode for high-performance use of replicated cores
  • Nexus Class 3+ interface
  • Interrupts
    • Replicated 16-priority controller
    • Replicated 16-channel eDMA controller
  • GPIOs individually programmable as input, output or special function
  • Three 6-channel general-purpose eTimer units
  • 2 FlexPWM units
    • Four 16-bit channels per module
  • Communications interfaces
    • 2 LINFlexD channels
    • 3 DSPI channels with automatic chip select generation
    • 2 FlexCAN interfaces (2.0B Active) with 32 message objects
    • FlexRay module (V2.1 Rev. A) with 2 channels, 64 message buffers and data rates up to 10 Mbit/s
  • Two 12-bit analog-to-digital converters (ADCs)
    • 16 input channels
    • Programmable cross triggering unit (CTU) to synchronize ADCs conversion with timer and PWM
  • Sine wave generator (D/A with low pass filter)
  • On-chip CAN/UART bootstrap loader
  • Single 3.0 V to 3.6 V voltage supply
  • Ambient temperature range –40 °C to 125 °C
  • Junction temperature range –40 °C to 150 °C