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SPC570S50E1CEFAY

SPC570S50E1CEFAY

SPC570S50E1DEFAR

Active

32-bit Power Architecture MCU for Automotive Chassis and Safety Applications

Quantity $ per Unit Savings
1 - 9$13.530%
10 - 24$12.2410%
25 - 99$11.6714%
100 - 249$10.1325%
250 - 499$9.6828%
500$8.8335%
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Out of stock
$13.53
Parameter NameParameter Value
Supply Voltage Min Volt3.0
Supply Voltage Max Volt5.5
Coree200z0
ECCN US5A991B4A
ECCN EUNEC
Packing TypeTape And Reel
ROHS Compliance GradeEcopack2
GradeAutomotive Safety
Package NameTQFP 64 10x10x1.0
Key features
  • AEC-Q100 qualified
  • High performance e200z0h dual core
    • 32-bit Power Architecture technology CPU
    • Core frequency as high as 80 MHz
    • Single issue 4-stage pipeline in-order execution core
    • Variable Length Encoding (VLE)
  • Up to 544 KB (512 KB code + 32 KB data, suitable for EEPROM emulation) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
  • Up to 48 KB on-chip general-purpose SRAM
  • Multi-channel direct memory access controller (eDMA paired in lockstep) with 16 channels
  • Comprehensive new generation ASILD safety concept
    • Safety of bus masters (core+INTC, DMA) by delayed lockstep approach
    • Safety of storage (Flash, SRAM) by mainly ECC
    • Safety of the data path to storage and periphery by mainly End-to-End EDC (E2E EDC)
    • Clock and power, generation and distribution, supervised by dedicated monitors
    • Fault Collection and Control Unit (FCCU) for collection and reaction to failure notifications
    • Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
    • Boot time MBIST and LBIST for latent faults
    • Check of safety mechanisms availability and error reaction path functionality by dedicated mechanisms
    • Safety of the periphery by application-level measures supported by replicated peripheral bridges and by LBIST
    • Further measures on dedicated peripherals (e.g. ADC supervisor)
    • Junction temperature sensor
    • 8-region system memory protection unit (SMPU) with process ID support (tasks isolation)
    • Enhanced SW watchdog
    • Cyclic redundancy check (CRC) unit
  • Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell
  • Nexus Class 3 debug and trace interface
  • Communication interfaces
    • 2 LINFlexD modules, 3 deserial serial per