SPC58EC80C3QMC1X

32-bit Power Architecture MCU for Automotive General Purpose Applications - Chorus family

Parameters

Supply Voltage Min Volt	3.0
Supply Voltage Max Volt	5.5
Operating Temp Min Celsius	-40.0
Core	Dual e200z4d
ECCN US	5A991.b.4.a
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Automotive Safety
Package Name	FPBGA 17X17X1.8 292 B0.55 P0.8

Description

The SPC584Cx and SPC58ECx microcontroller is the first in a new family of devices superseding the SPC564Cx and SPC56ECx family. SPC584Cx and SPC58ECx builds on the legacy of the SPC564Cx and SPC56ECx family, while introducing new features coupled with higher throughput to provide substantial...
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Key features

Key features
AEC-Q100 qualified High performance e200z420n3 dual core 32-bit Power Architecture technology CPU Core frequency as high as 180 MHz Variable Length Encoding (VLE) 4224 KB (4096 KB code flash + 128 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation 176 KB HSM dedicated flash memory (144 KB code + 32 KB data) 384 KB on-chip general-purpose SRAM (in addition to 128 KB core local data RAM: 64 KB included in each CPU) Multi-channel direct memory access controller (eDMA) with 64 channels 1 interrupt controller (INTC) Comprehensive new generation ASIL-B safety concept ASIL-B of ISO 26262 FCCU for collection and reaction to failure notifications Memory Error Management Unit (MEMU) for collection and reporting of error events in memories Cyclic redundancy check (CRC) unit Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC Body cross triggering unit (BCTU) Triggers ADC conversions from any eMIOS channel Triggers ADC conversions from up to 2 dedicated PIT_RTIs Enhanced modular IO subsystem (eMIOS): up to 64 timed I/O channels with 16-bit counter resolution Enhanced analog-to-digital converter system with: 3 independent fast 12-bit SAR analog converters 1 supervisor 12-bit SAR analog converter 1 10-bit SAR analog converter with STDBY mode support Communication interfaces 18 LINFlexD modules 8 deserial serial peripheral interface (DSPI) modules 8 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support Dual-channel FlexRay controller 1 ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008 Low power capabilities Versatile low power modes Ultra low power standby with RTC Smart Wake-up Unit for contact monitoring Fast wakeup schemes Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART Junction temperature range -40 °C to 150 °C

In stock

Quantity	$ per unit	Savings
1-9	$26.36	0%
10-24	$21.39	19%
25-50	$20.38	23%
50 +	Contact sales

$26.36

Parameters

Supply Voltage Min Volt	3.0
Supply Voltage Max Volt	5.5
Operating Temp Min Celsius	-40.0
Core	Dual e200z4d
ECCN US	5A991.b.4.a
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Automotive Safety
Package Name	FPBGA 17X17X1.8 292 B0.55 P0.8

Description

Key features

Key features
AEC-Q100 qualified High performance e200z420n3 dual core 32-bit Power Architecture technology CPU Core frequency as high as 180 MHz Variable Length Encoding (VLE) 4224 KB (4096 KB code flash + 128 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation 176 KB HSM dedicated flash memory (144 KB code + 32 KB data) 384 KB on-chip general-purpose SRAM (in addition to 128 KB core local data RAM: 64 KB included in each CPU) Multi-channel direct memory access controller (eDMA) with 64 channels 1 interrupt controller (INTC) Comprehensive new generation ASIL-B safety concept ASIL-B of ISO 26262 FCCU for collection and reaction to failure notifications Memory Error Management Unit (MEMU) for collection and reporting of error events in memories Cyclic redundancy check (CRC) unit Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC Body cross triggering unit (BCTU) Triggers ADC conversions from any eMIOS channel Triggers ADC conversions from up to 2 dedicated PIT_RTIs Enhanced modular IO subsystem (eMIOS): up to 64 timed I/O channels with 16-bit counter resolution Enhanced analog-to-digital converter system with: 3 independent fast 12-bit SAR analog converters 1 supervisor 12-bit SAR analog converter 1 10-bit SAR analog converter with STDBY mode support Communication interfaces 18 LINFlexD modules 8 deserial serial peripheral interface (DSPI) modules 8 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support Dual-channel FlexRay controller 1 ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008 Low power capabilities Versatile low power modes Ultra low power standby with RTC Smart Wake-up Unit for contact monitoring Fast wakeup schemes Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART Junction temperature range -40 °C to 150 °C