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    SPC58EG80E5P0H0Y

    SPC58EG80E5P0H0Y

    SPC58EG80E5QEC0X

    SPC58EG80E5QEC0X

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    SPC58EG80E5FEC0X

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    32-bit Power Architecture MCU for Automotive General Purpose Applications - Chorus family
    Learn More about SPC58EG80E5FEC0X

    Quantity $ per Unit Savings
    1 - 9$36.330%
    10 - 24$33.508%
    25 - 99$32.0012%
    100 - 249$28.6121%
    250 - 499$27.2925%
    500$25.9729%
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    Out of stock
    $36.33
    Parameter NameParameter Value
    Supply Voltage Min Volt3.0
    Supply Voltage Max Volt5.5
    Operating Temp Min Celsius-40.0
    Operating Temp Max Celsius105.0
    CoreDual e200z4d
    ECCN US5A991.b.4.a
    ECCN EUNEC
    Packing TypeTape And Reel
    RoHs compliantEcopack2
    GradeAutomotive Safety
    Package NameTQFP 144 20x20x1.0
    Key features
    • AEC-Q100 qualified
    • High performance e200z4 triple core:
      • 32-bit Power Architecture technology CPU
      • Core frequency as high as 180 MHz
      • Variable Length Encoding (VLE)
      • Floating Point, End-to-End Error Correction
    • 6582 KB (6144 KB code flash+ 256 KB data flash) on-chip flash memory:
      • supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
      • Supports read while read between the two code Flash partitions.
    • 608 KB on-chip general-purpose SRAM (in addition to 160 KB core local data RAM): 64KB in CPU_0, 64 KB in CPU_1 and 32 KB in CPU_2
    • 182 KB HSM dedicated flash memory (144 KB code + 32 KB data)
    • Multi-channel direct memory access controller (eDMA)
      • one eDMA with 64 channels
      • one eDMA with 32 channels
    • 1 interrupt controller (INTC)
    • Comprehensive new generation ASIL-D safety concept:
      • ASIL-D of ISO 26262
      • One CPU channel in lockstep
      • Logic BIST
      • FCCU for collection and reaction to failure notifications
      • Memory BIST
      • Cyclic redundancy check (CRC) unit
      • Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
    • Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC
    • Body cross triggering unit (BCTU)
      • Triggers ADC conversions from any eMIOS channel
      • Triggers ADC conversions from up to 2 dedicated PIT_RTIs
    • Enhanced modular IO subsystem (eMIOS): up to 64 timed IO channels with 16-bit counter resolution
    • Enhanced analog-to-digital converter system with:
      • 4 independent fast 12-bit SAR analog converters
      • One supervisor 12-bit SAR analog converter
      • One standby 10-bit SAR analog converter
    • Communication interfaces:
      • 18 LINFlexD modules
      • 10 de
    Associated Products