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SPC58NH92C3RMI0X

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32-bit Power Architecture MCU for Automotive General Purpose Applications - Chorus family

Quantity $ per Unit Savings
1 - 9$46.240%
10 - 24$43.147%
25 - 99$41.3411%
100 - 249$37.4619%
250 - 499$36.1722%
500$34.4526%
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$46.24
Parameter NameParameter Value
Operating RangeAutomotive
Supply Voltage Min Volt3.0
Supply Voltage Max Volt5.5
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius125.0
CoreTriple core
ECCN US5A991.b.4.a
ECCN EUNEC
Packing TypeTape And Reel
ROHS Compliance GradeEcopack2
GradeAutomotive Safety
Package NameFPBGA 17X17X1.8 302

The SPC58 H Line is a general-purpose MCU targeting high-end Body, Networking and Security applications. SPC58 H Line extends the Chorus Series of successful 40nm Automotive MCUs. and offers a seamless extension with compatible devices from 2 M up to 10 Mbytes Flash. Combining the 3x PowerPC cores (200Mhz) with a rich set of communication interfaces like 2x Ethernet, 16x ISO CAN FD and 24x LIN, it introduces new features to support Connected Gateway applications with Gigabit ethernet MAC for fast download, an hyperbus interface to extend the internal RAM and the eMMC interface to allow big data file storage.


To manage OTA update while the application keeps running, the 10 Mbyte flash can be programmed in background and its context swapped on reset.


The Smart Standby domain including RAM, RTC, ADC and a new low power SPI module increases the contact monitoring capability keeping the consumption extremely low (< 160 μA) and guaranteeing a fast start-up on wake-up event (< 500 μs).


The SPC58 H Line offers the highest performance and integrated devices available in high-efficiency pin count packages like eTQFP144 fully scalable up to FPBGA386. Designed according to ISO 26262, the SPC58 H Line supports ASIL-B/D offering 1 lockstep core as well as a EVITA full Security supporting asymmetric keys. With its 100 Mbit IPC the Chorus H Line is designed for system scalability coupling 2 Chorus H devices to build a system with 6 cores, 20 Mbytes flash and 2x Gigabit ethernet.

Key features
  • AEC-Q100 qualified
  • High performance e200z4 triple core:
    • 32-bit Power Architecture technology CPU
    • Core frequency as high as 200 MHz
    • Variable Length Encoding (VLE)
    • Floating Point, End-to-End Error Correction
  • 10496 KB (10240 KB code Flash + 256 KB data Flash) on-chip Flash memory:
    • Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
    • Supports read while read between the two code Flash partitions
    • Hardware support for Flash context switching (for FOTA with multi software versions)
  • 1088 KB on-chip general-purpose SRAM (in addition to 192 KB core local data RAM):
    • 64 KB in CPU_0, 64 KB in CPU_1 and 64 KB in CPU_2
  • 224 KB HSM dedicated Flash memory (192 KB code + 32 KB data)
  • Multi-channel direct memory access controller (eDMA):
    • One eDMA with 64 channels
    • One eDMA with 16 channels
  • One interrupt controller (INTC)
  • Comprehensive new generation ASIL-D safety concept:
    • ASIL-D of ISO 26262
    • One CPU channel in lockstep
    • Logic BIST
    • FCCU for collection and reaction to failure notifications
    • Memory BIST
    • Cyclic redundancy check (CRC) unit
    • Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
  • Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC
  • Body cross triggering unit (BCTU):
    • Triggers ADC conversions from any eMIOS channel
    • Triggers ADC conversions from up to 2 dedicated PIT_RTIs
  • Enhanced modular IO subsystem (eMIOS):
    • up to 96 timed IO channels with 16-bit counter resolution
  • Enhanced analog-to-digital converter system with:
    • 4 independent fast 12-bit SAR analog converters
    • One supervisor 12-bit SAR analog convert