SPC58NH92E7HMI0X

SPC58NH92E7HMI0X

SPC58NH92E7RMI0X

Active
32-bit Power Architecture MCU for Automotive General Purpose Applications - Chorus family
Quantity $ per Unit Savings
1 - 9$39.630%
10 - 24$36.568%
25 - 99$34.9312%
100 - 249$31.2221%
250 - 499$29.7825%
500$27.3831%
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Out of stock
$39.63
Parameter NameParameter Value
Supply Voltage Min Volt3.0
Supply Voltage Max Volt5.5
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius125.0
CoreTriple core
ECCN US5A991B4A
ECCN EU5A002A4
Packing TypeTape And Reel
ROHS Compliance GradeEcopack2
GradeAutomotive Safety
Package NameLQFP 176 24x24x1.4
Key features
  • AEC-Q100 qualified
  • High performance e200z4 triple core:
    • 32-bit Power Architecture technology CPU
    • Core frequency as high as 200 MHz
    • Variable Length Encoding (VLE)
    • Floating Point, End-to-End Error Correction
  • 10496 KB (10240 KB code Flash + 256 KB data Flash) on-chip Flash memory:
    • Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
    • Supports read while read between the two code Flash partitions
    • Hardware support for Flash context switching (for FOTA with multi software versions)
  • 1088 KB on-chip general-purpose SRAM (in addition to 192 KB core local data RAM):
    • 64 KB in CPU_0, 64 KB in CPU_1 and 64 KB in CPU_2
  • 224 KB HSM dedicated Flash memory (192 KB code + 32 KB data)
  • Multi-channel direct memory access controller (eDMA):
    • One eDMA with 64 channels
    • One eDMA with 16 channels
  • One interrupt controller (INTC)
  • Comprehensive new generation ASIL-D safety concept:
    • ASIL-D of ISO 26262
    • One CPU channel in lockstep
    • Logic BIST
    • FCCU for collection and reaction to failure notifications
    • Memory BIST
    • Cyclic redundancy check (CRC) unit
    • Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
  • Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC
  • Body cross triggering unit (BCTU):
    • Triggers ADC conversions from any eMIOS channel
    • Triggers ADC conversions from up to 2 dedicated PIT_RTIs
  • Enhanced modular IO subsystem (eMIOS):
    • up to 96 timed IO channels with 16-bit counter resolution
  • Enhanced analog-to-digital converter system with:
    • 4 independent fast 12-bit SAR analog converters
    • One supervisor 12-bit SAR analog convert