SR6P3C490D42FX0R

Stellar SR6 P3 line 32-bit Arm® Cortex®-R52+ automotive integration MCU 3x Cortex®-R52+ cores, 8 MB NVM (2x 7.5 MB "OTA X2") 1.3 MB RAM, with embedded virtualization, safety, and security

Parameters

Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	125.0
Core	Arm Cortex-R52+
ECCN US	5A991.b.4.a
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Automotive Safety Cybersecurity
Package Name	FPBGA 17X17X1.8 292 B0.55 P0.8

Description

Stellar integration MCUs have been designed to meet the requirements of domain controllers and ECUs with high integration requested in the architectures of connected updatable automated and electrified cars. They have superior real-time and safe performance (with highest ASIL-D capability)....
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Key features

Key features
AEC-Q100 SR6 integration MCUs: Have superior real-time and safe performance (with highest ASIL-D capability) Bring hardware-based virtualization technology to MCUs for simplified multiple software integrations at optimized performance Have built-in fast and cost-effective OTA reprogramming capability (with built-in dual-image storage) Offer high-speed security cryptographic services, for example for network authentication Cores 3 × 32-bit Cortex^®‑R52+ cores (all of them in lockstep configuration): Arm^® v8-R compliant Single precision floating-point unit (FPU) New privilege level for real-time virtualization 2 Cortex^®‑M4 multipurpose accelerators, one in lockstep configuration 4 eDMA engines in lockstep configuration Memories Up to 8 MB on-chip nonvolatile memory (NVM): PCM (phase-change memory) as nonvolatile memory 7.5 MB code NVM, with embedded memory replication for OTA (over-the-air) reprogramming with up to 2× 7.5 MB 512 KB HSM-dedicated code NVM 256 KB data NVM (128 KB + 128 KB dedicated to HSM) Up to 1328 KB on-chip general-purpose SRAM Security: 2^nd generation hardware security module Cybersecurity: ISO/SAE 21434 compliance (refer to the cybersecurity reference manual for details) On-chip high-performance security module with full support for e-safety vehicle intrusion protected applications (EVITA) Symmetric and asymmetric cryptography processor High-performance lock-stepped AES-light security subsystem for fast ASIL-D cryptographic services Safety: comprehensive new-generation ASIL-D safety concept New state-of-the-art safety measures at all levels of the architecture for most efficient implementation of ISO 26262 ASIL-D functionalities Complete hardware virtualization architecture built on Cortex^®‑R52+ new privilege mode (best-in-class software isolation, real-time support for multiple virtual machines/applications) Peripheral, I/O, and communication interfaces 16 LINFlexD modules 1 dual-channel FlexRay controller 10 queued serial peripheral interface (SPIQ) modules 2 microsecond channels (MSC) and 1 microsecond plus (MSC-Plus) channel 2 I²C interfaces 2 SENT modules (10 channels each) 2 PSI5 modules (1 channel each) Enhanced analog-to-digital converter system with: 6 separate 12-bit SAR analog converters (including one supervisor/safety ADC). 4 separate 9-bit SAR analog converters (2 channels each) with fast comparator mode 6 separate 16-bit sigma-delta analog converters with embedded DSP processor on each SD ADC Enhanced interconnection with GTM timer for autonomous ADC/GTM subsystem operation Advanced timed I/O capability: Generic timer module (GTM4124) High-resolution timer Communication interfaces: One 10/100/1000 Mbit/s Ethernet controller compliant with IEEE 802.3-2008: IPv4 and IPv6 checksum modules, AVB, VLAN 7 modular controller area network (MCAN) modules, and 1 time-triggered controller area network (M_TTCAN), all supporting flexible data rate (ISO CAN FD^®) 2 CAN XL^® interfaces

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Parameters

Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	125.0
Core	Arm Cortex-R52+
ECCN US	5A991.b.4.a
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Automotive Safety Cybersecurity
Package Name	FPBGA 17X17X1.8 292 B0.55 P0.8

Description

Key features

Key features
AEC-Q100 SR6 integration MCUs: Have superior real-time and safe performance (with highest ASIL-D capability) Bring hardware-based virtualization technology to MCUs for simplified multiple software integrations at optimized performance Have built-in fast and cost-effective OTA reprogramming capability (with built-in dual-image storage) Offer high-speed security cryptographic services, for example for network authentication Cores 3 × 32-bit Cortex^®‑R52+ cores (all of them in lockstep configuration): Arm^® v8-R compliant Single precision floating-point unit (FPU) New privilege level for real-time virtualization 2 Cortex^®‑M4 multipurpose accelerators, one in lockstep configuration 4 eDMA engines in lockstep configuration Memories Up to 8 MB on-chip nonvolatile memory (NVM): PCM (phase-change memory) as nonvolatile memory 7.5 MB code NVM, with embedded memory replication for OTA (over-the-air) reprogramming with up to 2× 7.5 MB 512 KB HSM-dedicated code NVM 256 KB data NVM (128 KB + 128 KB dedicated to HSM) Up to 1328 KB on-chip general-purpose SRAM Security: 2^nd generation hardware security module Cybersecurity: ISO/SAE 21434 compliance (refer to the cybersecurity reference manual for details) On-chip high-performance security module with full support for e-safety vehicle intrusion protected applications (EVITA) Symmetric and asymmetric cryptography processor High-performance lock-stepped AES-light security subsystem for fast ASIL-D cryptographic services Safety: comprehensive new-generation ASIL-D safety concept New state-of-the-art safety measures at all levels of the architecture for most efficient implementation of ISO 26262 ASIL-D functionalities Complete hardware virtualization architecture built on Cortex^®‑R52+ new privilege mode (best-in-class software isolation, real-time support for multiple virtual machines/applications) Peripheral, I/O, and communication interfaces 16 LINFlexD modules 1 dual-channel FlexRay controller 10 queued serial peripheral interface (SPIQ) modules 2 microsecond channels (MSC) and 1 microsecond plus (MSC-Plus) channel 2 I²C interfaces 2 SENT modules (10 channels each) 2 PSI5 modules (1 channel each) Enhanced analog-to-digital converter system with: 6 separate 12-bit SAR analog converters (including one supervisor/safety ADC). 4 separate 9-bit SAR analog converters (2 channels each) with fast comparator mode 6 separate 16-bit sigma-delta analog converters with embedded DSP processor on each SD ADC Enhanced interconnection with GTM timer for autonomous ADC/GTM subsystem operation Advanced timed I/O capability: Generic timer module (GTM4124) High-resolution timer Communication interfaces: One 10/100/1000 Mbit/s Ethernet controller compliant with IEEE 802.3-2008: IPv4 and IPv6 checksum modules, AVB, VLAN 7 modular controller area network (MCAN) modules, and 1 time-triggered controller area network (M_TTCAN), all supporting flexible data rate (ISO CAN FD^®) 2 CAN XL^® interfaces