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    ST8500TR

    ST8500TR

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    ST8500

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    Programmable power-line communication modem system-on-chip
    Learn More about ST8500

    Quantity $ per Unit Savings
    1 - 9$11.610%
    10 - 24$10.678%
    25 - 99$10.2312%
    100 - 249$9.0222%
    250 - 499$8.5826%
    500$8.3528%
    500 + Contact Sales
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    Parameter NameParameter Value
    ECCN US5A992.c
    ECCN EU5A002.a.2
    Packing TypeTray
    RoHs compliantEcopack2
    GradeIndustrial
    Package NameVFQFPN 56 7x7x1.0

    The ST8500 is a fully programmable power-line communication (PLC) modem system-on-chip (SoC), which is able to run any PLC protocol in the frequency band up to 500 kHz. The device architecture has been designed to target CENELEC EN50065, FCC and ARIB compliant applications supporting all major PLC protocol standards such as ITU G.9904 (PRIME), ITU G.9903 (G3-PLC®) and many other possible PLC protocol specifications and evolutions.

    Key features
    • Programmable power-line communication (PLC) modem system-on-chip
    • Integrated differential PLC analog front-end
      • PGA with automatic gain control and ADC
      • DAC with transmission pre-driver
      • Digital transmission level control
      • Zero-crossing comparator
      • Up to 500 kHz PLC signal bandwidth
    • High performance, fully programmable real time engine dedicated to PLC PHY and real time MAC protocol management (400 MHz max. frequency)
      • Dedicated code and data SRAM memories
    • Standard ARM© 32-bit Cortex™-M4F fully programmable core for protocol upper layers and peripheral management
      • 200 MHz maximum frequency
      • 256 kB of embedded SRAM for code and data
      • 96 kB of embedded SRAM for data
      • 8 kB of embedded shared RAM
      • Bootloader ROM memory
      • One time programmable (OTP) memory with dedicated areas available for secure keys and user information storage
      • Serial wire and JTAG interfaces
      • 24 multiplexed GPIOs
      • 4 general purpose timers
      • 1 flexible CRC calculation unit
      • 2 USART, 1 UART, 3 SPI, 1 I2C
    • Cryptographic engine
      • AES 128/192/256 engine
      • True random number generator
      • Pseudo random number generator
    • Clock management
      • 25 MHz external crystal for system clock
      • Integrated 25 MHz oscillator (XOSC) with frequency synthesizer (FS) and pre-scaler units to generate internal clock signals
    • Power management
      • 3.3 V external supply voltage for I/O and analog
      • 2.5 V internal linear regulator for analog
      • 1.1 V external supply voltage for digital
      • Normal, slow, doze and low power modes
    • Available in QFN56 (7x7x1 mm) package
    • -40 °C to +105 °C temperature range
    Associated Products