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Automotive HD Radio? baseband receiver - MRC enabled

Quantity $ per Unit Savings
1 - 9$19.960%
10 - 24$18.358%
25 - 99$17.5912%
100 - 249$15.5022%
250 - 499$14.7426%
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Parameter NameParameter Value
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius85.0
ECCN US3A991.a.2
Packing TypeTape And Reel
RoHs compliantEcopack2
Package NameLFBGA 168 12x12x1.4

The STA680M is an HD-radio base-band processor for car-radio applications. The STA680M functionality includes audio decompression and data processing, while multiple interfaces ensure flexible integration into the system.

The STA680M takes full advantage of HD 1.5 Radio benefits including CD-like audio quality from HD Radio FM broadcasts and FM-like audio quality using HD Radio AM, while program associated data or traffic information is received from the second channel or, alternatively, it features FM Maximum Ratio Combining Diversity for superior reception performance.

STA680M supports FM/AM analog/digital AAA algorithm by mean of specific FW.

Key features
  • AEC-Q100 qualified
  • IBOC (in-band on-channel) digital audio broadcast signal decoding for AM/FM hybrid and all-digital modes
  • Dual-channel HD 1.5 for background scanning and data services or FM Maximum Ratio Combining (MRC) Diversity algorithm
  • HD codec (HDC) audio decompression
  • Metadata support for HD Radio reception
  • MPS (main program service), SPS (supplemental program service) and PAD (program associated data) data decoding
  • Advanced HD Radio feature support:
    • Apple ID3 tag
    • Multicasting
    • Electronic program guide (EPG)
    • Real-time traffic
  • Automatic Audio Alignment (AAA) algorithm support
  • Variable input base-band data-rate I2S-like interface supporting 650, 675, 744.1875, 912 kS/s data rates
  • Secondary RF base-band interface for dual tuner applications
  • Glueless interface to Synchronous SDRAM addressing up to 512 Mbit of SDRAM in x16 configuration
  • Optional Serial Flash memory SPI interface for application code storage
  • IIS serial audio interface with programmable sample rate converter
  • Primary and secondary serial interfaces for host micro communication based on industry standard IIC and SPI
  • Several General purpose IOs
  • One Internal clock oscillator and two internal PLLs
  • External clock input
  • 1.2 V core supply; 3.3 V I/O supply