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    STA8100GATR

    STA8100GATR

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    STA8100GA

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    Teseo V Multi frequency GNSS receiver
    Learn More about STA8100GA

    Quantity $ per Unit Savings
    1 - 9$13.630%
    10 - 24$12.528%
    25 - 99$12.0212%
    100 - 249$10.5822%
    250 - 499$10.0626%
    500$9.4231%
    500 + Contact Sales
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    Out of stock
    $13.63
    Parameter NameParameter Value
    Operating RangeAutomotive
    Supply Voltage Min Volt1.71
    Supply Voltage Max Volt3.6
    Operating Temp Min Celsius-40.0
    Operating Temp Max Celsius105.0
    CoreArm Cortex-M7
    ECCN US7A994
    ECCN EUNEC
    Packing TypeTray
    RoHs compliantEcopack2
    GradeAutomotive
    Package NameLFBGA 8X8X1.7 81 PITCH 0.8 BALL

    STA8100GA is part of the Teseo V family.


    STA8100GA is a multi-band multi-constellation positioning receiver IC able to manage all the GNSS constellations such as GPS, Galileo, Glonass, BeiDou, NAVIC (former IRNSS) and QZSS, in L1, L2, L5 and E6 frequency bands.


    Key features
    • AEC-Q100 qualified
    • STMicroelectronics 5th generation positioning receiver with 80 tracking channels and 4 fast acquisition channels compatible with 6 constellations: GPS, Galileo, GLONASS, BeiDou, QZSS, NAVIC (former IRNSS)
    • Dual band L1 and L5 single chip solution
    • Triple band capability with external RF STA5635A
    • SBAS systems: WAAS, EGNOS, MSAS, GAGAN, BeiDou
    • Code phase, carrier phase, doppler frequency measurement
    • Antenna sensing
    • PPS output
    • Notch filter for anti-jamming
    • ARM® Cortex® M7 core:
      • Maximum clock frequency 314 MHz
      • 16 KB I-cache and 16 KB D-cache
      • 64 KB I-TCM and 384 KB D-TCM, core clock speed
      • Nested vector interrupt controller
      • JTAG debugging capability
      • 256 Kbyte system RAM
    • 32 channels DMA
    • Memory interfaces:
      • SFC (Octal/Quad serial flash controller, SDR)
      • SD multimedia card
    • Serial interfaces:
      • 3 x UART
      • Synchronous serial port (SPI supported)
      • I2C
      • 2 x multi mode serial interfaces
      • 2 x CAN controllers
    • Core peripherals:
      • 2 x multi timer units
      • Watchdog timer
      • 1 x extended function timers
      • 32 kHz oscillator real time clock
      • AES decipher hardware accelerator
    • Power management unit, with separate power supply domain and on-chip LDO and high voltage/low voltage monitors:
      • Backup voltage domain 1.7 to 3.6 V with LDO for always-on core supply and HV/LV detectors, and dedicated IO-ring0
      • Main voltage domain 1.7 to 3.6 V with LDO for switchable logic domain and HV/LV detectors for 85 °C maximum ambient temperature operations or 1.2 V +/ - 5 % external voltage supply for 105 °C maximum ambient temperature operations
      • Separate RF domain with dedicated LDO
      • IO-ring1 1.8 or 3.3 V capable, and dedica