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STA8135G

STA8135G

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STA8135GTR

Teseo V family industrial triple-band multi-constellation GNSS precise engine receiver

Operating RangeIndustrial
Supply Voltage Min Volt1.71
Supply Voltage Max Volt3.6
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius85.0
CoreArm Cortex-M7
ECCN US7A994
ECCN EUNEC
Packing TypeTape And Reel
RoHs compliantEcopack2
GradeIndustrial
Package NameTFBGA 7X11X1.2 160 F16X10 0.65P

The STA8135G is part of the Teseo V family and it is a multi-band multi-constellation positioning receiver IC able to manage all the GNSS constellations such as GPS, Galileo, GLONASS, BeiDou, NAVIC (former IRNSS) and QZSS, in L1, L2, L5, and E6 frequency bands.

Key features
  • STMicroelectronics 5th generation positioning receiver with 80 tracking channels and 4 fast acquisition channels compatible with 6 constellations: GPS, Galileo, GLONASS, BeiDou, QZSS, NAVIC (former IRNSS)
  • Triple band L1, L2, L5, E6 and L-band single package solution
  • SBAS systems: WAAS, EGNOS, MSAS, GAGAN, BeiDou
  • Code phase, carrier phase, doppler frequency measurement
  • Antenna sensing
  • PPS output
  • Notch filter for anti-jamming
  • ARM® Cortex® M7 core:
    • Maximum clock frequency 314 MHz
    • 16 kB I-cache and 16 kB D-cache
    • 64 kB I-TCM and 384 kB D-TCM, core clock speed
    • Nested vector interrupt controller
    • JTAG debugging capability
    • 256 Kbyte system RAM
  • 32-channel DMA
  • Memory interfaces:
    • SFC (Octal/Quad serial flash controller, SDR)
    • SD multimedia card
  • Serial interfaces:
    • 3 x UART
    • Synchronous serial port (SPI supported)
    • I2C
    • 2x multimode serial interfaces
    • 2x CAN controllers
  • Core peripherals:
    • 2x multi-timer units
    • Watchdog timer
    • 1x extended function timers
    • 32 kHz oscillator real-time clock
    • AES decipher hardware accelerator
  • Power management unit, with separate power supply domain and on-chip LDO and high voltage/low voltage monitors:
    • Backup voltage domain 1.62 to 3.6 V with LDO for always-on core supply and HV/LV detectors, and dedicated IO-ring0
    • Main voltage domain 1.62 to 3.6 V with LDO for switchable logic domain and HV/LV detectors for 85 °C maximum ambient temperature operations
    • Separate RF domain with dedicated LDO
    • IO-ring1 1.8 or 3.3 V capable, and dedicated 1.8 V LDO
    • IO-ring2 3.3 V ±10% capable
    • Fail-safe GPIOs available
  • Secure-digital multimedia memory card interfaces (SDMMC)
  • USB 2.0 full speed (12 Mb/s) with integrated physical layer transceiver
  • ESD: 2 kV (HBM) and 500 V (CDM)
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Quantity $ per unit Savings
1-500$0.000%
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Operating RangeIndustrial
Supply Voltage Min Volt1.71
Supply Voltage Max Volt3.6
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius85.0
CoreArm Cortex-M7
ECCN US7A994
ECCN EUNEC
Packing TypeTape And Reel
RoHs compliantEcopack2
GradeIndustrial
Package NameTFBGA 7X11X1.2 160 F16X10 0.65P

The STA8135G is part of the Teseo V family and it is a multi-band multi-constellation positioning receiver IC able to manage all the GNSS constellations such as GPS, Galileo, GLONASS, BeiDou, NAVIC (former IRNSS) and QZSS, in L1, L2, L5, and E6 frequency bands.

Key features
  • STMicroelectronics 5th generation positioning receiver with 80 tracking channels and 4 fast acquisition channels compatible with 6 constellations: GPS, Galileo, GLONASS, BeiDou, QZSS, NAVIC (former IRNSS)
  • Triple band L1, L2, L5, E6 and L-band single package solution
  • SBAS systems: WAAS, EGNOS, MSAS, GAGAN, BeiDou
  • Code phase, carrier phase, doppler frequency measurement
  • Antenna sensing
  • PPS output
  • Notch filter for anti-jamming
  • ARM® Cortex® M7 core:
    • Maximum clock frequency 314 MHz
    • 16 kB I-cache and 16 kB D-cache
    • 64 kB I-TCM and 384 kB D-TCM, core clock speed
    • Nested vector interrupt controller
    • JTAG debugging capability
    • 256 Kbyte system RAM
  • 32-channel DMA
  • Memory interfaces:
    • SFC (Octal/Quad serial flash controller, SDR)
    • SD multimedia card
  • Serial interfaces:
    • 3 x UART
    • Synchronous serial port (SPI supported)
    • I2C
    • 2x multimode serial interfaces
    • 2x CAN controllers
  • Core peripherals:
    • 2x multi-timer units
    • Watchdog timer
    • 1x extended function timers
    • 32 kHz oscillator real-time clock
    • AES decipher hardware accelerator
  • Power management unit, with separate power supply domain and on-chip LDO and high voltage/low voltage monitors:
    • Backup voltage domain 1.62 to 3.6 V with LDO for always-on core supply and HV/LV detectors, and dedicated IO-ring0
    • Main voltage domain 1.62 to 3.6 V with LDO for switchable logic domain and HV/LV detectors for 85 °C maximum ambient temperature operations
    • Separate RF domain with dedicated LDO
    • IO-ring1 1.8 or 3.3 V capable, and dedicated 1.8 V LDO
    • IO-ring2 3.3 V ±10% capable
    • Fail-safe GPIOs available
  • Secure-digital multimedia memory card interfaces (SDMMC)
  • USB 2.0 full speed (12 Mb/s) with integrated physical layer transceiver
  • ESD: 2 kV (HBM) and 500 V (CDM)