STHV1600L

16 channels ±100 V, ±2/4 A, 5/3-level RTZ, high-speed ultrasound pulser with integrated transmit beamformer

Parameters

ECCN US	EAR99
ECCN EU	NEC
Packing Type	Tray
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	LFBGA10X10X1.4 144 12SQ P.8 B.46

Description

This monolithic, high-speed transmitter features 16 independent channels with built-in digital beamforming, that generates 5-Level high voltage pulses (up to ±100 V) suitable to excite multiple channels of an ultrasound transducer.Each analog channel structure integrates an active RTZ circuit...
Read More

Key features

Key features
0 to 200 V peak-to-peak output signal Up to 30 MHz operating frequency Gate driver self-biased architecture; no filtering capacitors required Pulsed wave (PW) mode operation: 5/3 level output ±2 A / ±4 A source and sink current Continuous wave (CW) mode operation: 150 mW power consumption/channel 270 fs RMS jitter (100 Hz-20 kHz) -147 dBc/Hz @ 1 kHz phase noise Elastography mode operation Fully integrated real clamping-to-ground function 11 Ω synchronous active clamp ±2 A source and sink current Fully integrated T/R switch 9 Ω ON resistance 28 pF parasitic capacitance Compliant with receiver multiplexing function Auxiliary integrated circuits Noise blocking diode function Recirculation current protection Anti-memory feature Thermal protection Undervoltage protection and bias supply checks Programmable power management to optimize the performance into a probe TX Beamforming Programmable channels delay for beam-steering and beam-focusing Clock frequency up to 200 MHz Delay from 0 to 327 µs with 5 ns resolution at 200MHz 425 ns minimum delay table writing time Embedded volatile memory to store transmission patterns 64 kbit (256 rows x 16 bits per channel) Waveform compression and repetition algorithm Easy driving control Device control via serial interface Few input signals to drive several devices Diagnostic interrupt output Single trigger input with anti-glitch to manage TX/RX Checksum and parity check Very low thermal resistance Latch-up free thanks to HV SOI technology Only a few passive components required differential or rail-to-rail single-ended digital inputs (e.g. LVDS, LVPECL, VML, CML or CMOS)

Out of Stock

Quantity	$ per unit	Savings
1-4	$66.04	0%
5-9	$64.06	0%
10-24	$62.46	0%
25-49	$60.58	0%
50-99	$58.77	0%
100-249	$54.73	0%
250-500	$53.09	0%
500 +	Contact sales

$0.00

Parameters

ECCN US	EAR99
ECCN EU	NEC
Packing Type	Tray
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	LFBGA10X10X1.4 144 12SQ P.8 B.46

Description

Key features

Key features
0 to 200 V peak-to-peak output signal Up to 30 MHz operating frequency Gate driver self-biased architecture; no filtering capacitors required Pulsed wave (PW) mode operation: 5/3 level output ±2 A / ±4 A source and sink current Continuous wave (CW) mode operation: 150 mW power consumption/channel 270 fs RMS jitter (100 Hz-20 kHz) -147 dBc/Hz @ 1 kHz phase noise Elastography mode operation Fully integrated real clamping-to-ground function 11 Ω synchronous active clamp ±2 A source and sink current Fully integrated T/R switch 9 Ω ON resistance 28 pF parasitic capacitance Compliant with receiver multiplexing function Auxiliary integrated circuits Noise blocking diode function Recirculation current protection Anti-memory feature Thermal protection Undervoltage protection and bias supply checks Programmable power management to optimize the performance into a probe TX Beamforming Programmable channels delay for beam-steering and beam-focusing Clock frequency up to 200 MHz Delay from 0 to 327 µs with 5 ns resolution at 200MHz 425 ns minimum delay table writing time Embedded volatile memory to store transmission patterns 64 kbit (256 rows x 16 bits per channel) Waveform compression and repetition algorithm Easy driving control Device control via serial interface Few input signals to drive several devices Diagnostic interrupt output Single trigger input with anti-glitch to manage TX/RX Checksum and parity check Very low thermal resistance Latch-up free thanks to HV SOI technology Only a few passive components required differential or rail-to-rail single-ended digital inputs (e.g. LVDS, LVPECL, VML, CML or CMOS)