STM32C092GBU6

Mainstream Arm Cortex-M0+ MCU with 128 Kbytes of Flash memory, 30 Kbytes RAM, 48 MHz CPU, 4x USART, timers, ADC, comm. I/F, 2-3.6V

Parameters

Supply Voltage Min Volt	2.0
Supply Voltage Max Volt	3.6
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	85.0
Core	Arm Cortex-M0+
ECCN US	3A991.a.2
ECCN EU	NEC
Packing Type	Tray
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	UFQFPN 28 4x4x0.6 mm

Description

The STM32C091xB/xC STM32C092xB/xC mainstream microcontrollers are based on high-performance Arm® Cortex®-M0+ 32-bit RISC core operating at up to 48 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains...
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Key features

Key features
Includes ST state-of-the-art patented technology Core: Arm^® 32-bit Cortex^®-M0+ CPU, frequency up to 48 MHz -40°C to 85°C/105°C/125°C operating temperature Memories Up to 256 Kbytes of flash memory with protection and securable area Up to 36 Kbytes of SRAM with hardware parity check CRC calculation unit Reset and power management Voltage range: 2.0 V to 3.6 V Power-on / power-down reset (POR/PDR) Programmable brownout reset (BOR) Low-power modes: Sleep, Stop, Standby, Shutdown Clock management 4 to 48 MHz crystal oscillator 32 kHz crystal oscillator with calibration Internal 48 MHz RC oscillator (±1 %) Internal 32 kHz RC oscillator (±5 %) Up to 61 fast I/Os All mappable on external interrupt vectors All 5 V-tolerant 7-channel DMA controller with flexible mapping 12-bit, 0.4 µs ADC (up to 19 ext. channels) Conversion range: 0 to 3.6 V 10 timers: 16-bit for advanced motor control, one 32-bit timer and five 16-bit general-purpose, two watchdogs, SysTick timer Calendar RTC with alarm Communication interfaces Two I²C-bus interface supporting Fast-mode Plus (1 Mbit/s) with extra current sink; one supporting SMBus/PMBus™ and wake-up from Stop mode Four USARTs with master/slave synchronous SPI; one supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wake-up feature Two SPIs (24 Mbit/s) with 4- to 16-bit programmable bitframe, one multiplexed with I²S interface; four extra SPIs through USARTs One FDCAN controller (STM32C092xx only) Development support: serial wire debug (SWD) 96-bit unique ID All packages ECOPACK2 compliant

Out of Stock

Quantity	$ per unit	Savings
1-9	$2.78	0%
10-24	$1.81	35%
25-99	$1.64	41%
100-249	$1.38	50%
250-499	$1.30	53%
500	$1.14	59%
500 +	Contact sales

$2.78

Parameters

Supply Voltage Min Volt	2.0
Supply Voltage Max Volt	3.6
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	85.0
Core	Arm Cortex-M0+
ECCN US	3A991.a.2
ECCN EU	NEC
Packing Type	Tray
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	UFQFPN 28 4x4x0.6 mm

Description

Key features

Key features
Includes ST state-of-the-art patented technology Core: Arm^® 32-bit Cortex^®-M0+ CPU, frequency up to 48 MHz -40°C to 85°C/105°C/125°C operating temperature Memories Up to 256 Kbytes of flash memory with protection and securable area Up to 36 Kbytes of SRAM with hardware parity check CRC calculation unit Reset and power management Voltage range: 2.0 V to 3.6 V Power-on / power-down reset (POR/PDR) Programmable brownout reset (BOR) Low-power modes: Sleep, Stop, Standby, Shutdown Clock management 4 to 48 MHz crystal oscillator 32 kHz crystal oscillator with calibration Internal 48 MHz RC oscillator (±1 %) Internal 32 kHz RC oscillator (±5 %) Up to 61 fast I/Os All mappable on external interrupt vectors All 5 V-tolerant 7-channel DMA controller with flexible mapping 12-bit, 0.4 µs ADC (up to 19 ext. channels) Conversion range: 0 to 3.6 V 10 timers: 16-bit for advanced motor control, one 32-bit timer and five 16-bit general-purpose, two watchdogs, SysTick timer Calendar RTC with alarm Communication interfaces Two I²C-bus interface supporting Fast-mode Plus (1 Mbit/s) with extra current sink; one supporting SMBus/PMBus™ and wake-up from Stop mode Four USARTs with master/slave synchronous SPI; one supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wake-up feature Two SPIs (24 Mbit/s) with 4- to 16-bit programmable bitframe, one multiplexed with I²S interface; four extra SPIs through USARTs One FDCAN controller (STM32C092xx only) Development support: serial wire debug (SWD) 96-bit unique ID All packages ECOPACK2 compliant