STM32C531KCU6

Mainstream Arm Cortex-M33 MCU, 144 MHz, 256 KB flash, 64 KB RAM, I3C

Parameters

Supply Voltage Min Volt	2.7
Supply Voltage Max Volt	3.6
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	85.0
Core	Arm Cortex-M33
ECCN US	3A991.a.2
ECCN EU	NEC
Packing Type	Tray
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	UFQFPN 32 5x5x0.55 mm

Description

The STM32C53xxx devices are general purpose microcontrollers family (STM32C5 series) based on the high‑performance Arm® Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 144 MHz.The Cortex®-M33 core features a single‑precision floating‑point unit (FPU) that...
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Key features

Key features
Includes ST state-of-the-art patented technology. Core 32-bit Arm^® Cortex^®-M33 CPU with FPU, frequency up to 144 MHz, MPU, and DSP instructions Benchmarks ART Accelerator 8-Kbyte instruction cache allowing 0-wait-state execution from flash and up to CPU maximum speed Memories Up to 256‑Kbyte flash memory with ECC, 2 banks read-while-write 64-Kbyte SRAM including 32 Kbytes with ECC 64-Kbyte user data flash memory, 2 banks 4.5-Kbyte OTP (one-time programmable) Clock, reset, and supply management 2.7 V to 3.6 V application supply and I/O POR, PDR, and PVD Embedded regulator (LDO) Internal oscillators: 144 MHz HSI (with ± 1% accuracy over temperature range [-20°C : 130°C]) 160/144/100 MHz PSI 32 kHz LSI External oscillators: 4 to 50 MHz HSE 32.768 kHz LSE Low-power modes: Sleep, Stop, and Standby DMA controller to offload the CPU 2 x LPDMA with 8 channels (4 + 4) Analog 1 × 12-bit ADC (12 external channels and 2 internal), up to 2.25 MSPS 2 × 12-bit DACs 2 × comparators 1 × Operational amplifier Up to 10 timers 6 × 16-bit (including 2 × 16-bit advanced motor controls, 1 × low-power 16-bit timer available in Stop mode) and 1 × 32-bit timers 2 × watchdogs 1 × SysTick timer RTC with hardware calendar, alarms, and calibration Communication interfaces Up to 1 × I2C FM+ interface (SMBus/PMBus) Up to 1 × I3C Up to 2 × USARTs (ISO7816 interface, LIN, IrDA, modem control), 2 × UARTs, and 1 × LPUART Up to 2 × SPIs with muxed with full‑duplex I2S for audio class accuracy via external clock and up to 2 × additional SPIs from 2 × USARTs when configured in synchronous mode 2 × FDCANs 1 × USB 2.0 full-speed host and device Low-power modes Sleep, Stop, and Standby modes Up to 52 I/O ports with interrupt capability Security HASH hardware accelerator (SHA-1, SHA-224, SHA-256, HMAC) True random number generator, NIST SP800-90B compliant 96-bit unique ID Flexible life-cycle scheme with RDP and password-protected regression Mathematical coprocessor CORDIC for trigonometric functions acceleration Bootloader support on USART, FDCAN, USB, and SPI interfaces All packages are ECOPACK2 compliant.

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Parameters

Supply Voltage Min Volt	2.7
Supply Voltage Max Volt	3.6
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	85.0
Core	Arm Cortex-M33
ECCN US	3A991.a.2
ECCN EU	NEC
Packing Type	Tray
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	UFQFPN 32 5x5x0.55 mm

Description

Key features

Key features
Includes ST state-of-the-art patented technology. Core 32-bit Arm^® Cortex^®-M33 CPU with FPU, frequency up to 144 MHz, MPU, and DSP instructions Benchmarks ART Accelerator 8-Kbyte instruction cache allowing 0-wait-state execution from flash and up to CPU maximum speed Memories Up to 256‑Kbyte flash memory with ECC, 2 banks read-while-write 64-Kbyte SRAM including 32 Kbytes with ECC 64-Kbyte user data flash memory, 2 banks 4.5-Kbyte OTP (one-time programmable) Clock, reset, and supply management 2.7 V to 3.6 V application supply and I/O POR, PDR, and PVD Embedded regulator (LDO) Internal oscillators: 144 MHz HSI (with ± 1% accuracy over temperature range [-20°C : 130°C]) 160/144/100 MHz PSI 32 kHz LSI External oscillators: 4 to 50 MHz HSE 32.768 kHz LSE Low-power modes: Sleep, Stop, and Standby DMA controller to offload the CPU 2 x LPDMA with 8 channels (4 + 4) Analog 1 × 12-bit ADC (12 external channels and 2 internal), up to 2.25 MSPS 2 × 12-bit DACs 2 × comparators 1 × Operational amplifier Up to 10 timers 6 × 16-bit (including 2 × 16-bit advanced motor controls, 1 × low-power 16-bit timer available in Stop mode) and 1 × 32-bit timers 2 × watchdogs 1 × SysTick timer RTC with hardware calendar, alarms, and calibration Communication interfaces Up to 1 × I2C FM+ interface (SMBus/PMBus) Up to 1 × I3C Up to 2 × USARTs (ISO7816 interface, LIN, IrDA, modem control), 2 × UARTs, and 1 × LPUART Up to 2 × SPIs with muxed with full‑duplex I2S for audio class accuracy via external clock and up to 2 × additional SPIs from 2 × USARTs when configured in synchronous mode 2 × FDCANs 1 × USB 2.0 full-speed host and device Low-power modes Sleep, Stop, and Standby modes Up to 52 I/O ports with interrupt capability Security HASH hardware accelerator (SHA-1, SHA-224, SHA-256, HMAC) True random number generator, NIST SP800-90B compliant 96-bit unique ID Flexible life-cycle scheme with RDP and password-protected regression Mathematical coprocessor CORDIC for trigonometric functions acceleration Bootloader support on USART, FDCAN, USB, and SPI interfaces All packages are ECOPACK2 compliant.