STM32C552VET6

Mainstream Arm Cortex-M33 MCU, 144 MHz, 512 KB flash, 128 KB RAM, I3C, FDCAN

Parameters

Supply Voltage Min Volt	2.7
Supply Voltage Max Volt	3.6
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	85.0
Core	Arm Cortex-M33
ECCN US	3A991.a.2
ECCN EU	NEC
Packing Type	Tray
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	LQFP 100 14x14x1.4 mm

Description

The STM32C55xxx devices are general purpose microcontrollers family (STM32C5 Series) based on the high‑performance Arm® Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 144 MHz.The Cortex®-M33 core features a single‑precision floating‑point unit (FPU), that...
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Key features

Key features
Includes ST state-of-the-art patented technology. Core 32-bit Arm^® Cortex^®-M33 CPU with FPU, frequency up to 144 MHz, MPU, and DSP instructions Benchmarks ART Accelerator 8-Kbyte instruction cache enables 0-wait-state execution from flash memory at the CPU's maximum speed Memories Up to 512‑Kbyte flash memory with ECC, 2 banks read-while-write 128-Kbyte SRAM including 64-Kbyte with ECC 64-Kbyte flash memory area for software EEPROM emulation 4.5-Kbyte OTP (one-time programmable) Clock, reset, and supply management 2.7 V to 3.6 V application supply and I/O POR, PDR, and PVD Embedded regulator (LDO) Internal oscillators: 144 MHz HSI (with +/- 1% accuracy over temperature range [-20 °C : 130°C]), 160/144/100 MHz PSI, 32 kHz LSI External oscillators: 4 to 50 MHz HSE, 32.768 kHz LSE Low-power modes: Sleep, Stop, and Standby DMA controller to offload the CPU 2 x LPDMA with 12 channels (8 + 4) Analog 2 × 12-bit ADC (19 external channels and 2 internal), up to 2.25 MSPS, or up to 4.5 MSPS in dual interleaved mode 1 × 12-bit DAC (with output buffer) 1 × comparator (with configurable set of inputs) Up to 15 timers 9 × 16-bit (including 2 × 16-bit advanced motor control, 1 × low-power 16-bit timer available in Stop mode) and 2 × 32-bit timers 2 × watchdogs 1 × SysTick timer RTC with hardware calendar, alarms, and calibration Communication interfaces Up to 2 × I2C FM + interfaces (SMBus/PMBus) 1 × I3C Up to 3 × USARTs (ISO7816 interface, LIN, IrDA, modem control), 2 × UARTs, and 1 × LPUART Up to 3 × SPIs with full‑duplex I2S for audio-class accuracy through external clock, and up to 3 × additional SPIs derived from 3 × USARTs when configured in synchronous mode 1 × FDCAN 1 × USB 2.0 full-speed host and device Low-power modes Sleep, Stop, and Standby modes Up to 86 I/O ports with interrupt capability HASH (SHA-1, SHA-224, SHA-256), HMAC Mathematical coprocessor CORDIC for trigonometric functions acceleration 1 × True random number generator Bootloader support on USART, FDCAN, USB, and SPI interfaces Flexible life-cycle scheme with RDP and password-protected regression 96-bit unique ID All packages are ECOPACK2 compliant.

In stock

Quantity	$ per unit	Savings
1-9	$2.83	0%
10-24	$2.12	25%
25-99	$1.75	38%
100-249	$1.68	41%
250-500	$1.64	42%
500 +	Contact sales

$2.83

Parameters

Supply Voltage Min Volt	2.7
Supply Voltage Max Volt	3.6
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	85.0
Core	Arm Cortex-M33
ECCN US	3A991.a.2
ECCN EU	NEC
Packing Type	Tray
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	LQFP 100 14x14x1.4 mm

Description

Key features

Key features
Includes ST state-of-the-art patented technology. Core 32-bit Arm^® Cortex^®-M33 CPU with FPU, frequency up to 144 MHz, MPU, and DSP instructions Benchmarks ART Accelerator 8-Kbyte instruction cache enables 0-wait-state execution from flash memory at the CPU's maximum speed Memories Up to 512‑Kbyte flash memory with ECC, 2 banks read-while-write 128-Kbyte SRAM including 64-Kbyte with ECC 64-Kbyte flash memory area for software EEPROM emulation 4.5-Kbyte OTP (one-time programmable) Clock, reset, and supply management 2.7 V to 3.6 V application supply and I/O POR, PDR, and PVD Embedded regulator (LDO) Internal oscillators: 144 MHz HSI (with +/- 1% accuracy over temperature range [-20 °C : 130°C]), 160/144/100 MHz PSI, 32 kHz LSI External oscillators: 4 to 50 MHz HSE, 32.768 kHz LSE Low-power modes: Sleep, Stop, and Standby DMA controller to offload the CPU 2 x LPDMA with 12 channels (8 + 4) Analog 2 × 12-bit ADC (19 external channels and 2 internal), up to 2.25 MSPS, or up to 4.5 MSPS in dual interleaved mode 1 × 12-bit DAC (with output buffer) 1 × comparator (with configurable set of inputs) Up to 15 timers 9 × 16-bit (including 2 × 16-bit advanced motor control, 1 × low-power 16-bit timer available in Stop mode) and 2 × 32-bit timers 2 × watchdogs 1 × SysTick timer RTC with hardware calendar, alarms, and calibration Communication interfaces Up to 2 × I2C FM + interfaces (SMBus/PMBus) 1 × I3C Up to 3 × USARTs (ISO7816 interface, LIN, IrDA, modem control), 2 × UARTs, and 1 × LPUART Up to 3 × SPIs with full‑duplex I2S for audio-class accuracy through external clock, and up to 3 × additional SPIs derived from 3 × USARTs when configured in synchronous mode 1 × FDCAN 1 × USB 2.0 full-speed host and device Low-power modes Sleep, Stop, and Standby modes Up to 86 I/O ports with interrupt capability HASH (SHA-1, SHA-224, SHA-256), HMAC Mathematical coprocessor CORDIC for trigonometric functions acceleration 1 × True random number generator Bootloader support on USART, FDCAN, USB, and SPI interfaces Flexible life-cycle scheme with RDP and password-protected regression 96-bit unique ID All packages are ECOPACK2 compliant.