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Mainstream Arm Cortex-M0+ 32-bit MCU, up to 512KB Flash, 144KB RAM, 6x USART, timers, ADC, DAC, comm. I/Fs, AES, RNG, 1.7-3.6V

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1 - 9$6.840%
10 - 24$6.1410%
25 - 99$5.8115%
100 - 249$5.0426%
250 - 499$4.7730%
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Parameter NameParameter Value
Supply Voltage Min Volt1.7
Supply Voltage Max Volt3.6
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius85.0
CoreArm Cortex-M0+
ECCN US5A992.c
Packing TypeTray
RoHs compliantEcopack2
Package NameUFQFPN 48 7x7x0.55 mm

The STM32G0C1xC/xE mainstream microcontrollers are based on high-performance Arm® Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains and ready for the Internet of Things (IoT) solutions.

The devices incorporate a memory protection unit (MPU), high-speed embedded memories (144 Kbytes of SRAM and up to 512 Kbytes of Flash program memory with read protection, write protection, proprietary code protection, and securable area), DMA, an extensive range of system functions, enhanced I/Os, and peripherals. The devices offer standard communication interfaces (three I2Cs, three SPIs / two I2S, one HDMI CEC, one full-speed USB, two FD CANs, and six USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels, one 12-bit DAC with two channels, three fast comparators, an internal voltage reference buffer, a low-power RTC, an advanced control PWM timer running at up to double the CPU frequency, six general-purpose 16-bit timers with one running at up to double the CPU frequency, a 32-bit general-purpose timer, two basic timers, two low-power 16-bit timers, two watchdog timers, and a SysTick timer. The devices provide a fully integrated USB Type-C Power Delivery controller.

The devices embed AES hardware accelerator and true random number generator (RNG).

The devices operate within ambient temperatures from -40 to 125°C and with supply voltages from 1.7 V to 3.6 V. Optimized dynamic consumption combined with a comprehensive set of power-saving modes, low-power timers and low-power UART, allows the design of low-power applications.

VBAT direct battery input allows keeping RTC and backup registers powered.

The devices come in packages with 32 to 100 pins.

Key features
  • Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 64 MHz
  • -40°C to 85°C/105°C/125°C operating temperature
  • Memories
    • Up to 512 Kbytes of Flash memory with protection and securable area, two banks, read-while-write support
    • 144 Kbytes of SRAM (128 Kbytes with HW parity check)
  • CRC calculation unit
  • Reset and power management
    • Voltage range: 1.7 V to 3.6 V
    • Separate I/O supply pin (1.6 V to 3.6 V)
    • Power-on/Power-down reset (POR/PDR)
    • Programmable Brownout reset (BOR)
    • Programmable voltage detector (PVD)
    • Low-power modes:Sleep, Stop, Standby, Shutdown
    • VBAT supply for RTC and backup registers
  • Clock management
    • 4 to 48 MHz crystal oscillator
    • 32 kHz crystal oscillator with calibration
    • Internal 16 MHz RC with PLL option (±1 %)
    • Internal 32 kHz RC oscillator (±5 %)
  • Up to 94 fast I/Os
    • All mappable on external interrupt vectors
    • Multiple 5 V-tolerant I/Os
  • 12-channel DMA controller with flexible mapping
  • 12-bit, 0.4 µs ADC (up to 16 ext. channels)
    • Up to 16-bit with hardware oversampling
    • Conversion range: 0 to 3.6V
  • Two 12-bit DACs, low-power sample-and-hold
  • Three fast low-power analog comparators, with programmable input and output, rail-to-rail
  • 15 timers (two 128 MHz capable): 16-bit for advanced motor control, one 32-bit and six 16-bit general-purpose, two basic 16-bit, two low-power 16-bit, two watchdogs, SysTick timer
  • Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown
  • Communication interfaces
    • Three I2C-bus interfaces supporting Fast-mode Plus (1 Mbit/s) with extra current sink, two supporting SMBus/PMBus and wakeup from Stop mode
    • Six USARTs with master/slave synchronous SPI; three supporting ISO7816 interface, LIN