STM32H7B0IBK6Q

STM32H7B0IBK6Q

STM32H7B0IBT6

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High-performance and DSP with DP-FPU, Arm Cortex-M7 MCU with 128KBytes of Flash memory, 1376 KB SRAM, 280 MHz CPU, L1 cache, graphic accelerations, external memory interfaces and large set of peripherals

Quantity $ per Unit Savings
1 - 9$12.500%
10 - 24$11.508%
25 - 99$11.0212%
100 - 249$9.7122%
250 - 500$9.2326%
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$12.50
Parameter NameParameter Value
Supply Voltage Min Volt1.62
Supply Voltage Max Volt3.6
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius85.0
CoreArm Cortex-M7
ECCN US5A992C
ECCN EU5A002A4
Packing TypeTray
ROHS Compliance GradeEcopack2
GradeIndustrial
Package NameLQFP 176 24x24x1.4 mm
Key features
  • Core
    • 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache allowing to fill one cache line in a single access from the 128-bit embedded Flash memory; frequency up to 280 MHz, MPU, 599 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
  • Memories
    • 128 Kbytes of Flash memory plus 1 Kbyte of OTP
    • ~1.4 Mbytes of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 1.18 Mbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain
    • 2x Octo-SPI memory interfaces with on-the-fly
      decryption, I/O multiplexing and support for serial PSRAM/NOR, Hyper RAM/Flash frame formats, running up to 140 MHz in SRD mode and up to 110 MHz in DTR mode
    • Flexible external memory controller with up to 32-bit data bus:
      • SRAM, PSRAM, NOR Flash memory clocked up to 125 MHz in Synchronous mode

      • SDRAM/LPSDR SDRAM,

      • 8/16-bit NAND Flash memory

    • CRC calculation unit
  • Security
    • ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access mode
  • General-purpose input/outputs
    • Up to 138 I/O ports with interrupt capability
      • Fast I/Os capable of up to 133 MHz

      • Up to 164 5 V-tolerant I/Os

  • Low-power consumption
    • Stop: down to 32 µA with full RAM retention
    • Standby: 2.8 µA (Backup SRAM OFF, RTC/LSE ON, PDR OFF)
    • VBAT: 0.8 µA with RTC and LSE ON
  • Clock management
    • Internal oscillators: 64 MHz HSI, 48 MHz RC, 4 MHz CSI, 32 kHz LSI
    • External oscillators: 4-50 MHz HSE, 32.768 kHz LSE
    • 3× PLLs (1 for the sy