STM32MP133FAG7

32-bit Arm Cortex-A7 1GHz MPU for Security

Parameters

Supply Voltage Min Volt	1.71
Supply Voltage Max Volt	3.6
Core	Arm Cortex-A7
ECCN US	5A992.c
ECCN EU	NEC
Packing Type	Tray
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	TFBGA 289 9x9x1.2 P 0.5 mm

Description

The STM32MP133C/F devices are based on the high-performance Arm® Cortex®-A7 32-bit RISC core operating at up to 1 GHz. The Cortex®-A7 processor includes a 32-Kbyte L1 instruction cache, a 32-Kbyte L1 data cache and a 128-Kbyte level2 cache. The Cortex®-A7 processor is a very energy-efficient...
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Key features

Key features
Includes ST state-of-the-art patented technology Core 32-bit Arm^® Cortex^®-A7 L1 32-Kbyte I / 32-Kbyte D 128-Kbyte unified level 2 cache Arm^® NEON™ and Arm^® TrustZone^® Memories External DDR memory up to 1 Gbyte up to LPDDR2/LPDDR3-1066 16-bit up to DDR3/DDR3L-1066 16-bit 168 Kbytes of internal SRAM: 128 Kbytes of AXI SYSRAM + 32 Kbytes of AHB SRAM and 8 Kbytes of SRAM in Backup domain Dual Quad-SPI memory interface Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC Security/safety Secure boot, TrustZone^® peripherals, 12 x tamper pins including 5 x active tampers Temperature, voltage, frequency and 32 kHz monitoring Reset and power management 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os) POR, PDR, PVD and BOR On-chip LDOs (USB 1.8 V, 1.1 V) Backup regulator (~0.9 V) Internal temperature sensors Low-power modes: Sleep, Stop, LPLV-Stop, LPLVStop2 and Standby DDR retention in Standby mode Controls for PMIC companion chip Clock management Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator 4 × PLLs with fractional mode General-purpose input/outputs Up to 135 secure I/O ports with interrupt capability Up to 6 wakeup Interconnect matrix 2 bus matrices 64-bit Arm^® AMBA^® AXI interconnect, up to 266 MHz 32-bit Arm^® AMBA^® AHB interconnect, up to 209 MHz 4 DMA controllers to unload the CPU 56 physical channels in total 1 x high-speed general-purpose master direct memory access controller (MDMA) 3 × dual-port DMAs with FIFO and request router capabilities for optimal peripheral management Up to 29 communication peripherals 5 × I²C FM+ (1 Mbit/s, SMBus/PMBus™) 4 x UART + 4 x USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave) 5 × SPI (50 Mbit/s, including 4 with full-duplex I²S audio class accuracy via internal audio PLL or external clock) 2 × SAI (stereo audio: I²S, PDM, SPDIF Tx) SPDIF Rx with 4 inputs 2 × SDMMC up to 8 bits (SD/e•MMC™/SDIO) 2 × CAN controllers supporting CAN FD protocol 2 × USB 2.0 high-speed Host or 1 × USB 2.0 high-speed Host+ 1 × USB 2.0 high-speed OTG simultaneously 2 x Ethernet MAC/GMAC IEEE 1588v2 hardware, MII/RMII/RGMII 6 analog peripherals 2 × ADCs with 12-bit max. resolution up to 5 Msps 1 x temperature sensor 1 x digital filter for sigma-delta modulator (DFSDM) with 4 channels and 2 filters Internal or external ADC reference V_REF+ Up to 24 timers and 2 watchdogs 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input 2 × 16-bit advanced timers 10 × 16-bit general-purpose timers (including 2 basic timers without PWM) 5 × 16-bit low-power timers Secure RTC with sub-second accuracy and hardware calendar 4 Cortex^®-A7 system timers (secure, nonsecure, virtual, hypervisor) 2 × independent watchdogs Hardware acceleration AES 128, 192, 256 DES/TDES AES 128, 256 with DPA protection PKA ECC/RSA with DPA protection AES 128 on-the-fly DRAM encryption and decryption HASH (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3), HMAC 1 x true random number generator (6 triple oscillators) 1 x CRC calculation unit Debug mode Arm^® CoreSight™ trace and debug: SWD and JTAG interfaces usable as GPIOs 4-Kbyte embedded trace buffer 3072-bit fuses including 96-bit unique ID, up to 1280 bits available for user and 256-bit HUK to protect AES 256 keys All packages are ECOPACK2 compliant

In stock

Quantity	$ per unit	Savings
1-9	$7.24	0%
10-15	$5.65	22%
15 +	Contact sales

$7.24

Parameters

Supply Voltage Min Volt	1.71
Supply Voltage Max Volt	3.6
Core	Arm Cortex-A7
ECCN US	5A992.c
ECCN EU	NEC
Packing Type	Tray
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	TFBGA 289 9x9x1.2 P 0.5 mm

Description

Key features

Key features
Includes ST state-of-the-art patented technology Core 32-bit Arm^® Cortex^®-A7 L1 32-Kbyte I / 32-Kbyte D 128-Kbyte unified level 2 cache Arm^® NEON™ and Arm^® TrustZone^® Memories External DDR memory up to 1 Gbyte up to LPDDR2/LPDDR3-1066 16-bit up to DDR3/DDR3L-1066 16-bit 168 Kbytes of internal SRAM: 128 Kbytes of AXI SYSRAM + 32 Kbytes of AHB SRAM and 8 Kbytes of SRAM in Backup domain Dual Quad-SPI memory interface Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC Security/safety Secure boot, TrustZone^® peripherals, 12 x tamper pins including 5 x active tampers Temperature, voltage, frequency and 32 kHz monitoring Reset and power management 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os) POR, PDR, PVD and BOR On-chip LDOs (USB 1.8 V, 1.1 V) Backup regulator (~0.9 V) Internal temperature sensors Low-power modes: Sleep, Stop, LPLV-Stop, LPLVStop2 and Standby DDR retention in Standby mode Controls for PMIC companion chip Clock management Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator 4 × PLLs with fractional mode General-purpose input/outputs Up to 135 secure I/O ports with interrupt capability Up to 6 wakeup Interconnect matrix 2 bus matrices 64-bit Arm^® AMBA^® AXI interconnect, up to 266 MHz 32-bit Arm^® AMBA^® AHB interconnect, up to 209 MHz 4 DMA controllers to unload the CPU 56 physical channels in total 1 x high-speed general-purpose master direct memory access controller (MDMA) 3 × dual-port DMAs with FIFO and request router capabilities for optimal peripheral management Up to 29 communication peripherals 5 × I²C FM+ (1 Mbit/s, SMBus/PMBus™) 4 x UART + 4 x USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave) 5 × SPI (50 Mbit/s, including 4 with full-duplex I²S audio class accuracy via internal audio PLL or external clock) 2 × SAI (stereo audio: I²S, PDM, SPDIF Tx) SPDIF Rx with 4 inputs 2 × SDMMC up to 8 bits (SD/e•MMC™/SDIO) 2 × CAN controllers supporting CAN FD protocol 2 × USB 2.0 high-speed Host or 1 × USB 2.0 high-speed Host+ 1 × USB 2.0 high-speed OTG simultaneously 2 x Ethernet MAC/GMAC IEEE 1588v2 hardware, MII/RMII/RGMII 6 analog peripherals 2 × ADCs with 12-bit max. resolution up to 5 Msps 1 x temperature sensor 1 x digital filter for sigma-delta modulator (DFSDM) with 4 channels and 2 filters Internal or external ADC reference V_REF+ Up to 24 timers and 2 watchdogs 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input 2 × 16-bit advanced timers 10 × 16-bit general-purpose timers (including 2 basic timers without PWM) 5 × 16-bit low-power timers Secure RTC with sub-second accuracy and hardware calendar 4 Cortex^®-A7 system timers (secure, nonsecure, virtual, hypervisor) 2 × independent watchdogs Hardware acceleration AES 128, 192, 256 DES/TDES AES 128, 256 with DPA protection PKA ECC/RSA with DPA protection AES 128 on-the-fly DRAM encryption and decryption HASH (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3), HMAC 1 x true random number generator (6 triple oscillators) 1 x CRC calculation unit Debug mode Arm^® CoreSight™ trace and debug: SWD and JTAG interfaces usable as GPIOs 4-Kbyte embedded trace buffer 3072-bit fuses including 96-bit unique ID, up to 1280 bits available for user and 256-bit HUK to protect AES 256 keys All packages are ECOPACK2 compliant