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STM32WB30CEU5A

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Ultra-low-power dual core Arm Cortex-M4 MCU 64 MHz, Cortex-M0+ 32 MHz with 512 Kbytes of Flash memory, Bluetooth LE 5.3, 802.15.4, Zigbee, Thread, Matter, AES-256

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$5.84
Parameter NameParameter Value
Supply Voltage Min Volt2.0
Supply Voltage Max Volt3.6
Operating Temp Min Celsius-10.0
Operating Temp Max Celsius85.0
Operating Voltage Min Volt2.0
Operating Voltage Max Volt3.6
CoreArm Cortex-M4
ECCN US5A992.c
ECCN EUNEC
Packing TypeTray
RoHs compliantEcopack2
GradeIndustrial
Package NameUFQFPN 48 7x7x0.55 mm

The STM32WB50CG and STM32WB30CE multiprotocol wireless and ultra-low-power device embeds a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification 5.2 or with IEEE 802.15.4-2011. It contains a dedicated Arm® Cortex®-M0+ for performing all the real-time low layer operation.


The devices are designed to be extremely low-power and are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. This core features a Floating point unit (FPU) single precision that supports all Arm®single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security.


Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors.


The devices embed high-speed memories (1 Mbyte of Flash memory for STM32WB50xx, 512 Kbytes for STM32WB30xx, 128 Kbytes of SRAM for STM32WB50xx, 96 Kbytes for STM32WB30xx) and an extensive range of enhanced I/Os and peripherals.


Direct data transfer between memory and peripherals and from memory to memory is supported by seven DMA channels with a full flexible channel mapping by the DMAMUX peripheral.


The devices feature several mechanisms for embedded Flash memory and SRAM: readout protection, write protection and proprietary code readout protection. Portions of the memory can be secured for Cortex® -M0+ exclusive access.


The AES encryption engine, PKA and RNG enable lower layer MAC and upper layer cryptography. A customer key storage feature may be used to keep the keys hidden.


The devices offer a fast 16-bit ADC.


These devices embed a low-power RTC, one advanced 16-bit timer, one general-purpose32-bit timer, two general-purpose 16-bit timers, and two 16-bit low-power timers.


The STM32WB50CG and STM32WB30CE also feature standard and advanced communication interfaces, namely one USART (ISO 7816, IrDA, Modbus and Smartcard mode), one I2C (SMBus/PMBus), one SPI up to 32 MHz.


The STM32WB50CG and STM32WB30CE operate in the -10 to +85 °C (+105 °C junction) temperature range from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes enables the design of low-power applications.


The devices include independent power supplies for analog input for ADC.


A VBAT dedicated supply allows the device to back up the LSE 32.768 kHz oscillator, the RTC and the backup registers, thus enabling the STM32WB50CG and STM32WB30CE to supply these functions even if the main VDD is not present through a CR2032-like battery, a Supercap or a small rechargeable battery.


The STM32WB50CG and STM32WB30CE are available in a 48-pin UFQFPN package.


Key features
  • Includes ST state-of-the-art patented technology
  • Radio
    • 2.4 GHz
    • RF transceiver supporting Bluetooth® 5.2 specification or IEEE 802.15.4-2011 PHY and MAC, supporting Thread and Zigbee® 3.0
    • RX sensitivity: -96 dBm (Bluetooth® Low Energy at 1 Mbps), -100 dBm (802.15.4)
    • Programmable output power up to +4 dBm with 1 dB steps
    • Integrated balun to reduce BOM
    • Support for 1 Mbps
    • Dedicated Arm® 32-bit Cortex® M0+ CPU for real-time Radio layer
    • Accurate RSSI to enable power control
    • Suitable for systems requiring compliance with radio frequency regulations ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66
    • Support for external PA
    • Available integrated passive device (IPD) companion chip for optimized matching solution (MLPF-WB-01E3)
  • Ultra-low-power platform
    • 2.0 to 3.6 V power supply
    • – 10 °C to +85 °C temperature range
    • 14 nA shutdown mode
    • 700 nA Standby mode + RTC + 32 KB RAM
    • 2.25 µA Stop mode + RTC + 128 KB RAM
    • Radio: Rx 7.9 mA / Tx at 0 dBm 8.8 mA
  • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 64 MHz, MPU, 80 DMIPS and DSP instructions
  • Performance benchmark
    • 1.25 DMIPS/MHz (Drystone 2.1)
    • 219.48 CoreMark® (3.43 CoreMark/MHz at 64 MHz)
  • Energy benckmark
    • 303 ULPMark™ CP score
  • Supply and reset management
    • Ultra-safe, low-power BOR (brownout reset) with five selectable thresholds
    • Ultra-low-power POR/PDR
    • Programmable voltage detector (PVD)
    • VBAT mode with RTC and backup registers
  • Clock sources
    • 32 MHz crystal oscillator with integrated trimming capac