STM32WBA25CEU7

2.4 GHz Wireless Arm Cortex-M33 MCU, 64 MHz, 512 KB flash, Bluetooth BLE 6.2, Zigbee, Thread, 802.15.4, Q-SPI, USB OTG, TZ

Parameters

Supply Voltage Min Volt	1.8
Supply Voltage Max Volt	3.6
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	105.0
Core	Arm Cortex-M33
ECCN US	5A992.c
ECCN EU	NEC
Packing Type	Tray
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	UFQFPN 48 7x7x0.55 mm

Description

The STM32WBA2xxx multiprotocol wireless and ultra-low-power devices embed a powerful and ultra-low-power 2.4 GHz RADIO compliant with the Bluetooth® LE specifications and with IEEE 802.15.4-2015. They contain a high-performance Arm® Cortex®-M33 32-bit RISC core. They operate at a frequency of up...
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The STM32WBA2xxx multiprotocol wireless and ultra-low-power devices embed a powerful and ultra-low-power 2.4 GHz RADIO compliant with the Bluetooth^® LE specifications and with IEEE 802.15.4-2015. They contain a high-performance Arm^® Cortex^®-M33 32-bit RISC core. They operate at a frequency of up to 64 MHz.

The devices integrate a 2.4 GHz RADIO supporting Bluetooth^® LE, Thread^®, and Zigbee^®. It provides support for an array of up to eight antennas and an external power amplifier. The PTA (packet traffic arbitration) interface is supported.

The Cortex^®-M33 core features a single-precision floating-point unit (FPU), supporting all the Arm single-precision data-processing instructions and all the data types. This core also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) that enhances the application security.

The devices embed high-speed memories (512 Kbytes of flash memory and 96 Kbytes of SRAM), one Quad-SPI memory interface, and a range of enhanced I/Os and peripherals connected to AHB and APB buses on the 32-bit multi-AHB bus matrix.

The devices offer a security foundation compliant with the TBSA (trusted-based security architecture) requirements from Arm. It embeds the necessary security features to implement a secure boot, secure data storage, and secure firmware update. A flexible life cycle is managed through multi-level readout protection and debug unlock with password.

Firmware hardware isolation is supported using securable peripherals, memories and I/Os, and privilege configuration of peripherals and memories.

The devices feature several protection mechanisms for embedded flash memory and SRAM: readout protection, write protection, secure, and hide protection areas.

The devices embed several peripherals reinforcing security: a fast AES coprocessor, a PKA (public key accelerator) with DPA resistance, a HASH hardware accelerator, and a true random number generator.

The devices offer active tamper detection and protection against transient perturbation attacks with several internal monitoring mechanisms generating secret data erasure in the case of an attack.

The devices offer one 12-bit ADC (2.5 Msps), a low-power RTC, one 32-bit and two 16-bit general-purpose timers, and two 16-bit low-power timers. They also feature standard and advanced communication interfaces, namely two I2Cs, one SPI, one SAI, one USART and one low-power UART, and one full-speed Host- and Device-capable USB. The feature set is product-dependent.

The devices operate in the -40 to 85 °C and -40 to 105 °C temperature ranges from a 1.71 to 3.6 V power supply.

The design of low-power applications is enabled by a comprehensive set of power-saving modes.

Many peripherals (including radio, communication, analog, and timer peripherals) can be functional and autonomous in Stop mode with direct memory access thanks to BAM (background autonomous mode) support.

Some independent power supplies are supported, like an analog independent supply input for ADC, a 3.3 V dedicated supply input for USB, and radio-dedicated supply inputs for the 2.4 GHz RADIO.

The devices offer three packages, up to 48 pins, with or without SMPS.

Key features

Key features
Includes ST state-of-the-art patented technology Ultra-low-power radio 2.4 GHz radio RF transceiver supporting Bluetooth^® LE, IEEE 802.15.4-2015 PHY and MAC, supporting Zigbee^® RX sensitivity: -96 dBm (Bluetooth^® LE at 1 Mbps), -100 dBm (IEEE 802.15.4 at 250 kbps) Programmable output power, up to +10 dBm with 1 dB steps Support for external PA Packet traffic arbitration Integrated balun to reduce BOM Suitable for systems requiring compliance with radio frequency regulations ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15, and ARIB STD-T66 Bluetooth^® LE LE 2M LE coded Direction finding LE power control Isochronous channels Extended advertising Periodic advertising LE secure connections LE audio Mesh networking Qualified against Bluetooth^® Core 6.0 Ultra-low-power with FlexPowerControl 1.71 to 3.6 V power supply -40 to 85/105 °C ambiant temperature range Autonomous peripherals with DMA, functional down to Stop 1 mode 110 nA Standby mode (7 wake-up pins) 490 nA Standby mode with 64-Kbyte SRAM 980 nA Standby mode with 64-Kbyte SRAM, 2.4 GHz radio, RTC 4.81 µA Stop 1 mode with 64-Kbyte SRAM, 2.4 GHz radio, RTC 21 µA/MHz Run mode Radio: Rx 3.58 mA/ Tx at 0 dBm 4.65 mA Core Arm^® 32-bit Cortex^®-M33 CPU with TrustZone^®, MPU, DSP, and FPU running at up to 64 MHz ART Accelerator 4-Kbyte instruction cache allowing 0-wait-state execution from flash memory (frequency up to 64 MHz, 96 DMIPS) Benchmarks 264 CoreMark^® (4.12 CoreMark/MHz) Memories 512-Kbyte flash memory with ECC and 10 kcycles 96-Kbyte SRAM, including 32 Kbytes with parity check 512-byte (32 rows) OTP One Quad-SPI memory interface Power management Embedded regulator LDO and SMPS step-down converter, supporting switch on-the-fly and voltage scaling Clock management 32 MHz crystal oscillator 32 kHz crystal oscillator (LSE) Internal low-power 32 kHz (±5%) RC Internal 16 MHz factory-trimmed RC (±1%) PLL for system clock, audio, USB, and ADC General-purpose input/output Up to 27 I/Os (most of them 5 V-tolerant) with interrupt capability Analog peripherals (independent supply) 12-bit ADC 2.5 Msps, up to 16-bit with hardware oversampling Communication peripherals One USB full-speed selectable host or device controller One SAI (serial audio interface) One USART (ISO 7816, IrDA, modem) One LPUART (ISO 7816, modem) One SPI Two I2Cs Fm+ (1 Mbit/s), SMBus/PMBus^® System peripherals Two 16-bit timers One 32-bit timer Two low-power 16-bit timers (available in Stop mode) Two SysTick timers RTC with hardware calendar and calibration One watchdog 8-channel DMA controller, functional in Stop mode Security and cryptography Arm^® TrustZone^® and securable I/Os, memories, and peripherals Flexible life cycle scheme with readout protection (RDP) and password protected debug Root of trust thanks to unique boot entry and secure hide protection area (HDP) Secure boot and secure firmware update AES accelerator Public key accelerator, ECC and RSA, SCA resistant HASH hardware accelerator True random number generator, NIST SP800-90B compliant 96-bit unique ID Antitamper protections Development support Serial wire debug (SWD), JTAG Embedded trace (ETM) All packages are ECOPACK2 compliant.

In stock

Quantity	$ per unit	Savings
1-9	$4.84	2%
10-24	$3.64	23%
25-99	$3.42	28%
100-249	$3.06	35%
250-499	$2.91	39%
500	$2.75	42%
500 +	Contact sales

$4.84

$4.74