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The STM6513 has two separate delayed Smart Reset inputs (SR0, SR1) which when taken low simultaneously provide three user-selectable delayed Smart Reset setup time (tSRC) options of 2 s, 6 s and 10 s. These are selected through a three-state TSR input pin: when connected to ground, tSRC= 2 s; when left open, tSRC= 6 s; when connected to VCC, tSRC= 10 s (all the times are minimum). There are two reset outputs, both going active simultaneously after both the Smart Reset inputs were held active for the selected tSRCdelay time. The first reset output, RST1, is active-high, push-pull; the second reset output, RST2, is active-low, open-drain requiring an external pull-up resistor. The duration of the output reset pulses is independently programmable: tREC1is user-programmable (by external capacitor CtREC), tREC2is factory-programmed to 210 ms (typ.), with the option of 360 ms typ. Additionally, the VCCis monitored and if it drops below the selected VRSTthreshold, both the reset outputs go active and remain so while VCCis below the VRSTthreshold, plus the defined duration of the reset pulse tRECon each output.