STM6520AQRRDG9F

The Smart Reset™ devices provide a useful feature that ensures inadvertent short reset push-button closures do not cause system resets. This is done by implementing extended Smart Reset™ input delay time (t_SRC) and combined push-button inputs, which together ensures a safe reset and eliminates the need for a specific dedicated reset button.

This reset configuration provides versatility and allows the application to discriminate between a software generated interrupt and a hard system reset. When the input push-buttons are connected to microcontroller interrupt inputs, and are closed for a short time, the processor can only be interrupted. If the system still does not respond properly, continuing to keep the push-buttons closed for the extended setup time t_SRCcauses a hard reset of the processor through the reset outputs.

The STM6520 has two combined delayed Smart Reset™ inputs (SR0, SR1) with two user-selectable delayed Smart Reset™ setup time (t_SRC) options of 7.5 s and 12.5 s typ., selected by a dual-state Smart Reset™ DSR input pin. When DSR is connected to ground, t_SRC= 7.5 s, when connected to V_CC, t_SRC= 12.5 s (typ.). There are two reset outputs, both going active simultaneously after both of the Smart Reset™ inputs were held active for the selected t_SRC delay time. The outputs remain asserted until either or both inputs go to inactive logic level (for this device the output reset pulse duration is fully push-button controlled, meaning neither fixed nor minimum reset pulse width, nor power-on reset pulse is implemented). The first reset output, RST1, is active-low, open-drain; the second reset output, RST2, is active-high, push-pull. The device fully operates over a broad V_CC range 1.65 to 5.5 V. Below 1.575 V typ. the inputs are ignored and outputs are deasserted; the deasserted reset output levels are then valid down to 1.0 V.