STM8S207M8T3BTR

Mainstream Performance line 8-bit MCU with 64 Kbytes Flash, 24 MHz CPU, integrated EEPROM

Parameters

Supply Voltage Min Volt	2.95
Supply Voltage Max Volt	5.5
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	125.0
Core	STM8
ECCN US	EAR99
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	LQFP 80 14x14x1.4 mm

Description

The STM8S20xxx performance line 8-bit microcontrollers offer from 32 to 128 Kbytes Flash program memory. They are referred to as high-density devices in the STM8S microcontroller family reference manual.All STM8S20xxx devices provide the following benefits: reduced system cost, performance...
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Key features

Key features
Core Max f_CPU: up to 24 MHz, 0 wait states @ f_CPU≤ 16 MHz Advanced STM8 core with Harvard architecture and 3-stage pipeline Extended instruction set Max 20 MIPS @ 24 MHz Memories Program: up to 128 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles Data: up to 2 Kbytes true data EEPROM; endurance 300 kcycles RAM: up to 6 Kbytes Clock, reset and supply management 2.95 to 5.5 V operating voltage Low power crystal resonator oscillator External clock input Internal, user-trimmable 16 MHz RC Internal low power 128 kHz RC Clock security system with clock monitor Wait, active-halt, & halt low power modes Peripheral clocks switched off individually Permanently active, low consumption power-on and power-down reset Interrupt management Nested interrupt controller with 32 interrupts Up to 37 external interrupts on 6 vectors Timers 2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM) Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization 8-bit basic timer with 8-bit prescaler Auto wakeup timer Window watchdog, independent watchdog Communications interfaces High speed 1 Mbit/s active beCAN 2.0B UART with clock output for synchronous operation - LIN master mode UART with LIN 2.1 compliant, master/slave modes and automatic resynchronization SPI interface up to 10 Mbit/s I²C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os Up to 68 I/Os on an 80-pin package including 18 high sink outputs Highly robust I/O design, immune against current injection Development support Single wire interface module (SWIM) and debug module (DM) 96-bit unique ID key for each device

Out of Stock

Quantity	$ per unit	Savings
1-999	$6.94	0%
1000-1999	$3.12	55%
2000-10000	$2.96	57%
10000 +	Contact sales

$6.94

Parameters

Supply Voltage Min Volt	2.95
Supply Voltage Max Volt	5.5
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	125.0
Core	STM8
ECCN US	EAR99
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	LQFP 80 14x14x1.4 mm

Description

Key features

Key features
Core Max f_CPU: up to 24 MHz, 0 wait states @ f_CPU≤ 16 MHz Advanced STM8 core with Harvard architecture and 3-stage pipeline Extended instruction set Max 20 MIPS @ 24 MHz Memories Program: up to 128 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles Data: up to 2 Kbytes true data EEPROM; endurance 300 kcycles RAM: up to 6 Kbytes Clock, reset and supply management 2.95 to 5.5 V operating voltage Low power crystal resonator oscillator External clock input Internal, user-trimmable 16 MHz RC Internal low power 128 kHz RC Clock security system with clock monitor Wait, active-halt, & halt low power modes Peripheral clocks switched off individually Permanently active, low consumption power-on and power-down reset Interrupt management Nested interrupt controller with 32 interrupts Up to 37 external interrupts on 6 vectors Timers 2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM) Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization 8-bit basic timer with 8-bit prescaler Auto wakeup timer Window watchdog, independent watchdog Communications interfaces High speed 1 Mbit/s active beCAN 2.0B UART with clock output for synchronous operation - LIN master mode UART with LIN 2.1 compliant, master/slave modes and automatic resynchronization SPI interface up to 10 Mbit/s I²C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os Up to 68 I/Os on an 80-pin package including 18 high sink outputs Highly robust I/O design, immune against current injection Development support Single wire interface module (SWIM) and debug module (DM) 96-bit unique ID key for each device