📢 Special June promo: $5.99 worldwide delivery until June 30th! No code or minimum order required. Shop now! 🛒



Dual mode MIPI CSI-2/SMIA CCP2 de-serializer

Quantity $ per Unit Savings
1 - 500$0.000%
Contact Sales
Out of stock
Parameter NameParameter Value
Operating Temp Min Celsius-25.0
Operating Temp Max Celsius70.0
Package Size3 x 3 x 1.0
Packing TypeTape And Reel
RoHs compliantEcopack2
Package NameVFBGA 49 3x3x1.0

The STMIPID02 is a dual mode MIPI CSI-2 / SMIA CCP2 de-serializer targeted at mobile camera phone applications. Manufactured using ST 65 nm process, it integrates two MIPI CSI-2 / SMIA CCP2 receivers. The STMIPID02 can then support the main and the second cameras of a mobile camera phone.

One of the two MIPI CSI-2 receivers is a dual lane receiver allowing connection to high resolution / high frame rate cameras.

The SMIA CCP2 compatible receivers share the same input balls as the MIPI CSI-2 receivers.

STMIPID02’s 12-bit parallel output interface is capable of outputting de-serialized pixel data at rates up to 200 MHz.

Pass through mode allows the STMIPID02 to be used as a standalone MIPI D-PHY physical layer device.

With this device a host with a standard 8-bit, 10-bit or 12-bit parallel input interface can be connected to camera modules with either a MIPI CSI-2 or a SMIA CCP2 low-voltage, fully differential bit-serial, low EMI interface.

There is an interrupt output for every MIPI CSI-2 short packet.

Power management is simplified by the presence of an integrated 1.2 V regulator to supply the MIPI D-PHY receiver and core logic.

The STMIPID02 is fully configurable via an I2C compatible slave control I/F.

Key features
  • Dual mode camera de-serializer
  • MIPI CSI-2 receivers
    • Two-camera interface support
    • One 1.6 Gbps dual data lane receiver for main camera with selectable 1/2 lane operation
    • One 800 Mbps single data lane receiver for second camera
    • Each MIPI D-PHY interface has a 400 MHz DDR clock lane
    • MIPI D-PHY Pass through mode
    • Selectable 0.81 or 0.9 D-PHY revision specification
  • SMIA CCP2 receivers
    • Two-camera interface support
    • 650 Mbps class 2 receivers with selectable data/clock and data/strobe operation
  • Support for MIPI CSI-2 and SMIA CCP2 RAW6, RAW7, RAW8 (generic), RAW10 and RAW12 Raw Bayer format data unpacking
  • Support for YUV, RGB and JPEG formats
  • Support for SMIA 8-10, 7-10, 6-10, 10-12,8-12, 7-12, and 6-12 DPCM/PCM decompression options
  • 1V8, 200 MHz,12-bit parallel output interface
  • HSYNC, VSYNC, and continuous PCLK output data qualification signal
  • Tristate-able output for dual camera systems
  • Error interrupt output (D-PHY and protocol)
  • MIPI CSI-2 short packet interrupt output
  • 2-wire 100/400 kHz control interface (I2C compatible slave) to configure D-PHY timeouts and pixel data unpacking/decompression options
  • Integrated power on reset cell
  • Digital power supply: 1.7 V to 1.9 V
  • Integrated 1.2 V regulator for D-PHY and core logic
  • VFBGA 49 ball, 3 mm x 3 mm x 1 mm, 0.4 mm pitch, 0.25 mm ball package
  • Lead-free RoHS compliant product