STNRG388A

Digital controller for power conversion applications with up to 6 programmable PWM generators, 96 MHz PLL

Parameters

Supply Voltage Min Volt	3.0
Supply Voltage Max Volt	5.5
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	105.0
ECCN US	3A991.a.2
ECCN EU	NEC
Packing Type	Tube
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	TSSOP 38

Description

STNRG devices are a part of the STNRG family of STMicroelectronics^® digital devices designed for advanced power conversion applications.

Key features

Key features
Up to 6 programmable PWM generators (SMED - “State Machine Event Driven”) 10 ns event detection and reaction Max.1.3 ns PWM resolution Single, coupled and two coupled operational modes Up to 3 internal/external events per SMED 4 analog comparators 4 internal 4-bit references Up to 4 external references Less than 50 ns propagation time Continuous comparison cycle Configurable hysteresis voltage levels ADCs (up to 8 channels) 10-bit precision, with operational amplifier to extend resolution to 12-bit equivalent Sequencer functionality Input impedance: 1 MW Configurable gain value: x1 and x4 Integrated microcontroller Advanced STM8^® core with Harvard architecture and 3-stage pipeline Max. f_CPU: 16 MHz Memories Flash and E²PROM with read while write (RWW) and error correction code (ECC) Program memory: 32 Kbytes Flash; data retention 15 years at 85 °C after 10 kcycles at 25 °C Data memory: 1 Kbyte true data E²PROM; data retention:15 years at 85 °C after 100 kcycles at 85 °C RAM: 6 Kbytes Clock management Internal 96 MHz PLL Low power oscillator circuit for external crystal resonator or direct clock input Internal, user-trimmable 16 MHz RC and low power 153.6 kHz RC oscillators Clock security system with clock monitor Basic peripherals System, auxiliary and basic timers IWDG/WWDG watchdog, AWU, ITC Reset and supply management Multiple low power modes (wait, slow, auto- wakeup, Halt) with user definable clock gating Low consumption power-on and power- down reset I/O Multifunction bidirectional GPIO with highly robust design, immune against current injection Fast digital input DIGIN, with configurable pull-up Communication interfaces UART asynchronous with SW flow control and bootloader support I²C master/slave fast-slow speed rate Operating temperature: -40 °C up to 105 °C. Configurable state machine generating a PWM signal More than 10.4 ns PWM native resolution Up to 1.3 ns PWM resolution when using SMED dithering 6 states available in each SMED: IDLE, S0, S1, S2, S3 plus a special HOLD state Transactions triggered by synchronous and asynchronous external events or an internal timer Each transaction can generate an interrupt Fifteen registers available to configure the state machine behavior Four 16-bit configurable time registers, one for each running state (T0, T1, T2, T3) Internal resources accessible through the processor interface Eight interrupt request lines Configurable ADC HW trigger request PWM pseudo open drain features configurable through GPIO1 registers GPIO0 [x] configured as input Hiz (where x = 1,0) DAC&x>_EN = '0' and CP&x>_EN_ERef = '1 of MSC_DACCTR available only &undefined&undefinedon the STNRG388A register.

Out of Stock

Quantity	$ per unit	Savings
1-9	$7.28	32%
10-24	$5.53	0%
25-99	$5.15	7%
100-249	$4.53	18%
250-499	$4.29	22%
500	$3.85	30%
500 +	Contact sales

$5.51

Parameters

Supply Voltage Min Volt	3.0
Supply Voltage Max Volt	5.5
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	105.0
ECCN US	3A991.a.2
ECCN EU	NEC
Packing Type	Tube
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	TSSOP 38

Description

STNRG devices are a part of the STNRG family of STMicroelectronics^® digital devices designed for advanced power conversion applications.

Key features

Key features
Up to 6 programmable PWM generators (SMED - “State Machine Event Driven”) 10 ns event detection and reaction Max.1.3 ns PWM resolution Single, coupled and two coupled operational modes Up to 3 internal/external events per SMED 4 analog comparators 4 internal 4-bit references Up to 4 external references Less than 50 ns propagation time Continuous comparison cycle Configurable hysteresis voltage levels ADCs (up to 8 channels) 10-bit precision, with operational amplifier to extend resolution to 12-bit equivalent Sequencer functionality Input impedance: 1 MW Configurable gain value: x1 and x4 Integrated microcontroller Advanced STM8^® core with Harvard architecture and 3-stage pipeline Max. f_CPU: 16 MHz Memories Flash and E²PROM with read while write (RWW) and error correction code (ECC) Program memory: 32 Kbytes Flash; data retention 15 years at 85 °C after 10 kcycles at 25 °C Data memory: 1 Kbyte true data E²PROM; data retention:15 years at 85 °C after 100 kcycles at 85 °C RAM: 6 Kbytes Clock management Internal 96 MHz PLL Low power oscillator circuit for external crystal resonator or direct clock input Internal, user-trimmable 16 MHz RC and low power 153.6 kHz RC oscillators Clock security system with clock monitor Basic peripherals System, auxiliary and basic timers IWDG/WWDG watchdog, AWU, ITC Reset and supply management Multiple low power modes (wait, slow, auto- wakeup, Halt) with user definable clock gating Low consumption power-on and power- down reset I/O Multifunction bidirectional GPIO with highly robust design, immune against current injection Fast digital input DIGIN, with configurable pull-up Communication interfaces UART asynchronous with SW flow control and bootloader support I²C master/slave fast-slow speed rate Operating temperature: -40 °C up to 105 °C. Configurable state machine generating a PWM signal More than 10.4 ns PWM native resolution Up to 1.3 ns PWM resolution when using SMED dithering 6 states available in each SMED: IDLE, S0, S1, S2, S3 plus a special HOLD state Transactions triggered by synchronous and asynchronous external events or an internal timer Each transaction can generate an interrupt Fifteen registers available to configure the state machine behavior Four 16-bit configurable time registers, one for each running state (T0, T1, T2, T3) Internal resources accessible through the processor interface Eight interrupt request lines Configurable ADC HW trigger request PWM pseudo open drain features configurable through GPIO1 registers GPIO0 [x] configured as input Hiz (where x = 1,0) DAC&x>_EN = '0' and CP&x>_EN_ERef = '1 of MSC_DACCTR available only &undefined&undefinedon the STNRG388A register.