STV0991FAH Active

Advanced HDR ISP with dedicated HW engines for video analytics and lens correction
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius105.0
Package Size10 x10 x 1.2
Packing TypeTray
ROHS Compliance GradeEcopack2
Package NameTFBGA 10X10 201L
Key Features
  • Self-contained, no external memory needed
  • Central system
    • ARM® Cortex-R4 CPU @500 MHz
    • 2 Mbytes of SRAM
    • 4 Mbytes of stacked Flash or 16 Mbyte external Flash with update via communication interfaces
    • emulated EEPROM
    • interrupt and DMA controllers
  • HDR on-the-fly image signal processing
    • 150 Mpixel/s effective throughput,up to 5 Mpixel and 22 bit front-end processing
    • global tone mapping
    • lens shading correction noise suppression, defective pixel repair, sharpening, adaptive color matrix, multiple scaling engines
    • image statistics engine for AEC/AWB
    • JPEG 8-bit/12-bit, 5/2.1 Mpixel @30 fps
    • H.264 baseline I,P, 2.1 Mpixel @30 fps
  • Video analytics accelerators
    • edge data extractor
    • optical flow generator
  • Lens distortion (for example fish-eye) correction
  • Graphics overlay
  • Code protection against hacking
  • Multi-camera synchronization support
  • Operation with quartz crystal or external clock
  • Interfaces
    • Serial (CSI-2) input
    • Parallel video input and output
    • RGMII/GMII, 2x SDIO, 2x SPI, 3x I2C, CAN, 6x LIN, multiple GPIOs with 4x ADC inputs
    • I2S in, I2S out, PDM for digital microphone
    • clock output for image sensor
  • ASIL-related features
  • Low power consumption
  • -40 °C to +105 °C operating temperature range (Ta)
  • AEC-Q100 grade 2 compliance

The STV0991 is a versatile system-on-chip device designed for automotive, security and a multitude of other camera applications. From video and audio input through HDR image signal processing, lens distortion correction, graphics overlay, video compression, video analytics acceleration, CPU, operating and non-volatile memory, media access controller, to video and audio outputs and communication interfaces, it comprises all elements to support compact, low bill-of-material and low energy-consumption camera applications. No external memory chips such as DRAM or Flash are required for its operation, predictive H.264 video encoding inclusive.

Video analytics accelerators unload the central CPU from intensive repetitive tasks. A graphics renderer unit compensates for perceptual distortion produced by wide-angle lenses (such as fish-eye) and inserts graphical and/or textual information over the video. Resulting ready-for-display video can be output as-is over the parallel or serial video output port, or real-time compressed for streaming out through one of: RGMII/GMII, SDIO or SPI interfaces. An audio signal can be input through either an I2S or a PDM input, processed by the CPU and inserted into the output data stream. A return audio channel is also supported, outputting the audio on an I2S output. Precise Time Protocol (PTP) support and other provisions on the die allow precise instant-of-exposure synchronization of cameras in a multi-camera system, independent of cable lengths. A cryptographic and hash unit permits protection of customer intellectual property embedded in their software. Flash content can be updated via communication interfaces, thus allowing non-intrusive customer firmware updates. A debug access port (DAP) helps users in their software development process. The application diagram suggests some of the applications possible through combining optional elements as required.

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