L9965A-TR

18 Cell Battery Management IC

The L9965A is an 18 channel battery cells monitoring and balancing IC.

Key features
AEC-Q100 qualified Temperature grade 1: –40 °C to +125 °C operating temperature range HBM ESD classification level 2 CDM ESD classification level C4B Full ISO26262 compliant, ASIL-D systems ready, documentation available Fully synchronized high accuracy measurements on cell voltage, busbar and stack voltage with dedicated ADC: Total error including aging and post soldering <1.4 mV at 3.3 V, -40 °C to 105 °C 16-bit resolution Cell range: -1 to 5.5 V Integrated digital filtering with programmable cutoff frequency from 3.3 kHz to 4.4 Hz Fully redundant architecture Cell and busbar support on every channel Dedicated busbar channel with ±1 V range Passive internal cell balancing up to 400 mA, supporting time-continuous and PWM modes, with automatic cool down based on external NTC sensing. Overcurrent protection during balancing is also available in low-power mode Integrated DC-DC converter for energy efficiency: Deep-sleep: <12 µA Cyclic WAKEUP mode: <20 µA Normal mode: <2 mA 10 configurable GPIO SPI controller and I2C controller peripherals for interfacing external EEPROMs and sensors SPI target for direct MCU interface Stackable architecture for high-voltage battery packs up to 59 devices Embedded NVM for configuration parameters storage and runtime configuration integrity check Ultrafast vertical interface peripheral for isolated communication Compatible with L9965C pack monitoring chip with a max desynchronization time of 7 µs at system level

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The L9965A is an 18 channel battery cells monitoring and balancing IC.

Key features
AEC-Q100 qualified Temperature grade 1: –40 °C to +125 °C operating temperature range HBM ESD classification level 2 CDM ESD classification level C4B Full ISO26262 compliant, ASIL-D systems ready, documentation available Fully synchronized high accuracy measurements on cell voltage, busbar and stack voltage with dedicated ADC: Total error including aging and post soldering <1.4 mV at 3.3 V, -40 °C to 105 °C 16-bit resolution Cell range: -1 to 5.5 V Integrated digital filtering with programmable cutoff frequency from 3.3 kHz to 4.4 Hz Fully redundant architecture Cell and busbar support on every channel Dedicated busbar channel with ±1 V range Passive internal cell balancing up to 400 mA, supporting time-continuous and PWM modes, with automatic cool down based on external NTC sensing. Overcurrent protection during balancing is also available in low-power mode Integrated DC-DC converter for energy efficiency: Deep-sleep: <12 µA Cyclic WAKEUP mode: <20 µA Normal mode: <2 mA 10 configurable GPIO SPI controller and I2C controller peripherals for interfacing external EEPROMs and sensors SPI target for direct MCU interface Stackable architecture for high-voltage battery packs up to 59 devices Embedded NVM for configuration parameters storage and runtime configuration integrity check Ultrafast vertical interface peripheral for isolated communication Compatible with L9965C pack monitoring chip with a max desynchronization time of 7 µs at system level