SPC564A80B4CFAR

32-bit Power Architecture MCU for Automotive Powertrain Applications

Parameters

Operating Range	Automotive
Supply Voltage Min Volt	4.5
Supply Voltage Max Volt	5.5
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	125.0
Core	e200z4d
ECCN US	5A991.b.4.a
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Automotive
Package Name	PBGA 324 23x23x1.82

Description

The microcontroller’s e200z4 host processor core is built on Power Architecture technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP).

Key features

Key features
150 MHz e200z4 Power Architecture core Variable length instruction encoding (VLE) Superscalar architecture with 2 execution units Up to 2 integer or floating point instructions per cycle Up to 4 multiply and accumulate operations per cycle Memory organization 4 MB on-chip flash memory with ECC and Read While Write (RWW) 192 KB on-chip RAM with standby functionality (32 KB) and ECC 8 KB instruction cache (with line locking), configurable as 2- or 4-way 14 + 3 KB eTPU code and data RAM 5 × 4 crossbar switch (XBAR) 24-entry MMU External Bus Interface (EBI) with slave and master port Fail Safe Protection 16-entry Memory Protection Unit (MPU) CRC unit with 3 sub-modules Junction temperature sensor Interrupts Configurable interrupt controller (with NMI) 64-channel DMA Serial channels 3 × eSCI 3 × DSPI (2 of which support downstream Micro Second Channel [MSC]) 3 × FlexCAN with 64 messages each 1 × FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC 1 × eMIOS 24 unified channels 1 × eTPU2 (second generation eTPU) 32 standard channels 1 × reaction module (6 channels with three outputs per channel) 2 enhanced queued analog-to-digital converters (eQADCs) Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external multiplexers 6 command queues Trigger and DMA support 688 ns minimum conversion time On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM) Nexus: Class 3+ for core; Class 1 for the eTPU JTAG (5-pin) Development Trigger Semaphore (DTS) Clock generation On-chip 4–40 MHz main oscillator On-chip FMPLL (frequency-modulated phase-locked loop) Up to 120 general purpose I/O lines Individually programmable as input, output or special function Programmable threshold (hysteresis) Power reduction mode: slow, stop and stand-by modes Flexible supply scheme 5 V single supply with external ballast Multiple external supply: 5 V, 3.3 V and 1.2 V Designed for LQFP176, LBGA208, PBGA324 and Known Good Die (KGD)

Out of Stock

Quantity	$ per unit	Savings
1-349	$30.56	0%
350-500	$22.96	25%
500 +	Contact sales

$30.56

Parameters

Operating Range	Automotive
Supply Voltage Min Volt	4.5
Supply Voltage Max Volt	5.5
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	125.0
Core	e200z4d
ECCN US	5A991.b.4.a
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Automotive
Package Name	PBGA 324 23x23x1.82

Description

Key features

Key features
150 MHz e200z4 Power Architecture core Variable length instruction encoding (VLE) Superscalar architecture with 2 execution units Up to 2 integer or floating point instructions per cycle Up to 4 multiply and accumulate operations per cycle Memory organization 4 MB on-chip flash memory with ECC and Read While Write (RWW) 192 KB on-chip RAM with standby functionality (32 KB) and ECC 8 KB instruction cache (with line locking), configurable as 2- or 4-way 14 + 3 KB eTPU code and data RAM 5 × 4 crossbar switch (XBAR) 24-entry MMU External Bus Interface (EBI) with slave and master port Fail Safe Protection 16-entry Memory Protection Unit (MPU) CRC unit with 3 sub-modules Junction temperature sensor Interrupts Configurable interrupt controller (with NMI) 64-channel DMA Serial channels 3 × eSCI 3 × DSPI (2 of which support downstream Micro Second Channel [MSC]) 3 × FlexCAN with 64 messages each 1 × FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC 1 × eMIOS 24 unified channels 1 × eTPU2 (second generation eTPU) 32 standard channels 1 × reaction module (6 channels with three outputs per channel) 2 enhanced queued analog-to-digital converters (eQADCs) Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external multiplexers 6 command queues Trigger and DMA support 688 ns minimum conversion time On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM) Nexus: Class 3+ for core; Class 1 for the eTPU JTAG (5-pin) Development Trigger Semaphore (DTS) Clock generation On-chip 4–40 MHz main oscillator On-chip FMPLL (frequency-modulated phase-locked loop) Up to 120 general purpose I/O lines Individually programmable as input, output or special function Programmable threshold (hysteresis) Power reduction mode: slow, stop and stand-by modes Flexible supply scheme 5 V single supply with external ballast Multiple external supply: 5 V, 3.3 V and 1.2 V Designed for LQFP176, LBGA208, PBGA324 and Known Good Die (KGD)