SPC574S64E3CEFAR

SPC574S64E3CEFAR

SPC574S64E3CEFAY

Active
32-bit Power Architecture MCU for Automotive Chassis and Safety Applications
Quantity $ per Unit Savings
1 - 9$14.340%
10 - 24$13.188%
25 - 99$12.6312%
100 - 249$11.1322%
250 - 499$10.5826%
500$9.9031%
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Out of stock
$14.34
Parameter NameParameter Value
Operating RangeAutomotive
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius125.0
CoreDual e200z4d
ECCN US5A991B4A
ECCN EUNEC
Packing TypeTray
ROHS Compliance GradeEcopack2
GradeAutomotive Safety
Package NameTQFP 100 14x14x1.0
Key features
  • AEC-Q100 qualified
  • High performance e200z4d dual core
    • 32-bit Power Architecture technology CPU
    • Core frequency as high as 140 MHz
    • Dual issue 5-stage pipeline in-order execution core
    • Variable Length Encoding (VLE)
    • Core MPU
    • Floating Point, End-to-End Error Correction
    • 8 KB instruction cache with error detection code
    • 32 KB local data RAM and 4 KB data cache along with 8 KB instruction cache
  • 1600 KB (1.5 MB code + 64 KB data) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
  • 128 KB on-chip RAM (96 KB on chip RAM + 32 KB local data RAM)
  • Multi-channel direct memory access controller (eDMA) with 32 channels
  • Comprehensive new generation ASILD safety concept
    • ASILD SEooC approach (Safety Element out of Context)
    • FCCU for collection and reaction to failure notifications
    • Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
    • End-to-end Error Correction Code (e2eECC) logic
    • Cyclic redundancy check (CRC) unit
  • 8 enhanced 12-bit SAR analog converters
    • 2 sets of: 3 ADCs and one supervisor ADC
    • 1.5 µs conversion time at 12 MHz
    • Up to 32 physical channels
    • Dual Programmable CTU
  • 4 general purpose eTimer units (6 channels each)
  • 4 FlexPWM units
    • 2 (4 channels each) used for motor control with hardware synchronization between the control systems
    • 2 (2 channels each) used for SWG emulation
  • Communication interfaces
    • 4 LINFlexD modules
    • 4 deserial serial peripheral interface (DSPI) modules
    • 2 MCAN interfaces with advanced shared memory scheme (808 x 32-bit words for MCAN0 and 520 x 32-bit words for MCAN1) and CAN-FD support
    • 1 FlexRay module with 2 channels, 128 message buffers
    • 2 SENT interfaces (3