SPC582B54E3L000X

32-bit Power Architecture MCU for Automotive General Purpose Applications - Chorus family

Parameters

Supply Voltage Min Volt	3.0
Supply Voltage Max Volt	5.5
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	125.0
Core	e200z2
ECCN US	5A991.b.4.a
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Automotive Safety
Package Name	TQFP 100 14x14x1.0

Description

The SPC582Bx microcontroller is the entry member of a new family of devices superseding the SPC560Bx family.SPC582Bx is built on the legacy of the SPC5x products, while introducing new features to answer the future requirements like the ASIL-B classification, high number of ISO CAN-FD channels, and...
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Key features

Key features
AEC-Q100 qualified High performance e200z2 single core 32-bit Power Architecture technology CPU Core frequency as high as 80 MHz Variable Length Encoding (VLE) Floating Point, End-to-End Error Correction 1088 KB (1024 KB code flash + 64 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation 96 KB on-chip general-purpose SRAM Multi-channel direct memory access controller (eDMA) with 16 channels 1 interrupt controller (INTC) Comprehensive new generation ASIL-B safety concept ASIL-B of ISO 26262 FCCU for collection and reaction to failure notifications Memory Error Management Unit (MEMU) for collection and reporting of error events in memories Cyclic redundancy check (CRC) unit End-to-end Error Correction Code (e2eECC) logic Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC Body cross triggering unit (BCTU) Triggers ADC conversions from any eMIOS channel Triggers ADC conversions from up to 2 dedicated PIT_RTIs 1 event configuration register dedicated to each timer event allows to define the corresponding ADC channel Synchronization with ADC to avoid collision 1 enhanced 12-bit SAR analog-to-digital converters Up to 27 channels enhanced diagnosis feature Communication interfaces 6 LINFlexD modules 4 deserial serial peripheral interface (DSPI) modules 7 MCAN interfaces with advanced shared memory scheme and ISO CAN FD support Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell Nexus Class 3 debug and trace interface Boot assist Flash (BAF) supports factory progr

Out of Stock

Quantity	$ per unit	Savings
1-9	$10.10	0%
10-24	$9.55	5%
25-99	$9.27	8%
100-249	$8.55	15%
250-499	$8.27	18%
500	$7.94	21%
500 +	Contact sales

$10.10

Parameters

Supply Voltage Min Volt	3.0
Supply Voltage Max Volt	5.5
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	125.0
Core	e200z2
ECCN US	5A991.b.4.a
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Automotive Safety
Package Name	TQFP 100 14x14x1.0

Description

Key features

Key features
AEC-Q100 qualified High performance e200z2 single core 32-bit Power Architecture technology CPU Core frequency as high as 80 MHz Variable Length Encoding (VLE) Floating Point, End-to-End Error Correction 1088 KB (1024 KB code flash + 64 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation 96 KB on-chip general-purpose SRAM Multi-channel direct memory access controller (eDMA) with 16 channels 1 interrupt controller (INTC) Comprehensive new generation ASIL-B safety concept ASIL-B of ISO 26262 FCCU for collection and reaction to failure notifications Memory Error Management Unit (MEMU) for collection and reporting of error events in memories Cyclic redundancy check (CRC) unit End-to-end Error Correction Code (e2eECC) logic Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC Body cross triggering unit (BCTU) Triggers ADC conversions from any eMIOS channel Triggers ADC conversions from up to 2 dedicated PIT_RTIs 1 event configuration register dedicated to each timer event allows to define the corresponding ADC channel Synchronization with ADC to avoid collision 1 enhanced 12-bit SAR analog-to-digital converters Up to 27 channels enhanced diagnosis feature Communication interfaces 6 LINFlexD modules 4 deserial serial peripheral interface (DSPI) modules 7 MCAN interfaces with advanced shared memory scheme and ISO CAN FD support Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell Nexus Class 3 debug and trace interface Boot assist Flash (BAF) supports factory progr