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SPC58NE84E7QMHAY

SPC58NE84E7QMHAY

SPC58NE84E7QMHAR

SPC58NE84E7QMHAR

SPC58NE84E7QMSAR

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32-bit Power Architecture MCU for High Performance Applications

Quantity $ per Unit Savings
1 - 9$46.010%
10 - 24$42.937%
25 - 50$41.1311%
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$46.01
Parameter NameParameter Value
Operating Temp Min Celsius-40.0
Coree200z4d
ECCN US5A991.b.4.a
ECCN EUNEC
Packing TypeTape And Reel
RoHs compliantEcopack2
GradeAutomotive Safety
Package NameLQFP 176 24x24x1.4

SPC58NExx family is the first member of the new SPC58NExx family of 32-bit Flash Automotive MCUs offering a hardware based solution able to answer both ISO26262 ASIL-D compliant and high-performance real-time system requirements for mid/high-end powertrain applications.


Note: This document is preliminary and subject to any change without notification.

Key features
  • Two 32-bit Power Architecture®VLE compliant CPU core (e200z4d), dual issue, one of them being paired in lockstep
    • Single-precision floating point operations
    • 8 kB I-Cache and 4 kB D-Cache
    • 16 kB local instruction SRAM and 64 kB local data SRAM
  • One 32-bit Power Architecture®VLE compliant CPU core (e200z4d), dual issue, paired in lockstep
    • Single-precision floating point operations
    • Lightweight Signal Processing Auxiliary Processing Unit (LSP APU) instruction support for digital signal processing (DSP)
    • 8 kB I-Cache
    • 16 kB local instruction SRAM and 32 kB local data SRAM
  • 6320 kB on-chip flash memory
    • Supporting EEPROM emulation (256 kB)
    • 2 Flash Controller supporting true Read-While-Read Flash access (RWR)
  • 608 kB on-chip general-purpose SRAM (+160 kB data RAM included in the CPUs)
  • Multi-channel direct memory access controller (eDMA) with 96 channels, paired in lock-step
  • Dual phase-locked loops, including one frequency-modulated
  • Hardware Security Module (HSM) to provide robust integrity checking of flash memory
  • Generic timer module (GTM)
    • Intelligent complex timer module
    • 144 channels (40 inputs/104 outputs)
    • 5 programmable fine grain multi-threaded cores
    • 61 kB of dedicated SRAM
    • Hardware support for engine control, motor control and safety related applications
  • Enhanced analog-to-digital converter system with:
    • 5 separate 12-bit SAR analog converters, 46 channels, 1.5 μs conversion time, TUE ±4 LSB
    • 3 separate 10-bit SAR analog converters, 16 channels, 1.0μs conversion time, TUE ±2 LSB
    • 6 separate 16-bit Sigma-Delta analog converters, 20 channels
  • 10 Deserial Serial Peripheral Interface (DSPI) modules, 18 LIN and UART communication interface (LINFlexD) modules, including 2 Micro Second Bus (MSB) channels