SPC58NN84E7RMHBR

32-bit Power Architecture MCU for High Performance Applications

Parameters

Operating Temp Min Celsius	-40.0
Core	e200z4d
ECCN US	5A991.b.4.a
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Automotive Safety
Package Name	LQFP 176 24x24x1.4

Description

The SPC58xNx microcontroller belongs to a family of devices superseding the SPC5x family. SPC58xNx is built on the legacy of the SPC5x family, while introducing new features coupled with higher throughput to provide substantial reduction of cost per feature and significant power and performance...
Read More

Key features

Key features
AEC-Q100 qualified 32-bit Power Architecture VLE compliant CPU cores: Five enhanced main e200z4256n3 cores, dual issue, two paired in lockstep Floating Point, End-to-End Error Correction 6576 KB (6288 KB code flash + 288 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation Supports read while read between the two code Flash partitions. 128 KB on-chip general-purpose SRAM (in addition to 384 KB included in the CPUs) 96-channel direct memory access controller (eDMA) Comprehensive new generation ASIL-D safety concept ASIL-D of ISO 26262 FCCU for collection and reaction to failure notifications Memory Error Management Unit (MEMU) for collection and reporting of error events in memories Cyclic redundancy check (CRC) unit Junction temperature range -40 °C to 165 °C Dual-channel FlexRay controller Hardware Security Module (HSM) GTM344 - generic timer module Intelligent complex timer module 144 channels (48 input and 96 output) 5 programmable fine grain multi-threaded cores 61 KB of dedicated RAM 24-bit wide channels Enhanced analog-to-digital converter system with: 1 supervisor 12-bit SAR analog converter 2 separate 10-bit SAR analog converter 4 separate fast 12-bit SAR analog converters 6 separate 16-bit Sigma-Delta analog converter with programmable decimation filters SAR ADC Queued digital interfaces for individual channel ordering and command sequencing Communication interfaces 7 LINFlexD modules 8 deserial serial peripheral interface (DSPI) modules 7 modular controller area network (MCAN) modules, and one time-triggered controller area network (M-TTCAN), all supporting flexible data rate (ISO CAN-FD) One Ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008 Flexible Power Supply options: External Regulators (1.2 V core, 3.3 V–5 V IO) Single internal SMPS regulator Nexus development interface (NDI) per IEEEISTO 5001-2003 standard, with some support for 2010 standard Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART

Out of Stock

Quantity	$ per unit	Savings
1	$36.40	0%
1 +	Contact sales

$36.40

Parameters

Operating Temp Min Celsius	-40.0
Core	e200z4d
ECCN US	5A991.b.4.a
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Automotive Safety
Package Name	LQFP 176 24x24x1.4

Description

Key features

Key features
AEC-Q100 qualified 32-bit Power Architecture VLE compliant CPU cores: Five enhanced main e200z4256n3 cores, dual issue, two paired in lockstep Floating Point, End-to-End Error Correction 6576 KB (6288 KB code flash + 288 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation Supports read while read between the two code Flash partitions. 128 KB on-chip general-purpose SRAM (in addition to 384 KB included in the CPUs) 96-channel direct memory access controller (eDMA) Comprehensive new generation ASIL-D safety concept ASIL-D of ISO 26262 FCCU for collection and reaction to failure notifications Memory Error Management Unit (MEMU) for collection and reporting of error events in memories Cyclic redundancy check (CRC) unit Junction temperature range -40 °C to 165 °C Dual-channel FlexRay controller Hardware Security Module (HSM) GTM344 - generic timer module Intelligent complex timer module 144 channels (48 input and 96 output) 5 programmable fine grain multi-threaded cores 61 KB of dedicated RAM 24-bit wide channels Enhanced analog-to-digital converter system with: 1 supervisor 12-bit SAR analog converter 2 separate 10-bit SAR analog converter 4 separate fast 12-bit SAR analog converters 6 separate 16-bit Sigma-Delta analog converter with programmable decimation filters SAR ADC Queued digital interfaces for individual channel ordering and command sequencing Communication interfaces 7 LINFlexD modules 8 deserial serial peripheral interface (DSPI) modules 7 modular controller area network (MCAN) modules, and one time-triggered controller area network (M-TTCAN), all supporting flexible data rate (ISO CAN-FD) One Ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008 Flexible Power Supply options: External Regulators (1.2 V core, 3.3 V–5 V IO) Single internal SMPS regulator Nexus development interface (NDI) per IEEEISTO 5001-2003 standard, with some support for 2010 standard Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART