SR6G7C6A2C42FX0R

Stellar SR6 G7 line, 32-bit Arm® Cortex®-R52+ automotive integration MCU 6x Cortex®-R52+ cores, 20.5 MB NVM (2x 19.5 MB "OTA X2") 8.9 MB RAM, with embedded virtualization, safety and security

Parameters

Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	105.0
Core	Arm Cortex-R52+
ECCN US	5A991.b.4.a
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Automotive Safety Cybersecurity
Package Name	FPBGA 21.3X21.3X1.8 476 P.8 B.55

Description

Stellar integration MCUs have been designed to meet the requirements of domain controllers and ECUs with high integration requested in the architectures of connected updatable automated and electrified cars. They have superior real-time and safe performance (with highest ASIL-D capability)....
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Key features

Key features
AEC-Q100 SR6 integration MCUs: Have superior real-time and safe performance (with highest ASIL-D capability) Bring hardware-based virtualization technology to MCUs for simplified multiple software integrations at optimized performance Have built-in fast and cost-effective OTA reprogramming capability (with built-in dual-image storage) Offer high-speed security cryptographic services, for example for network authentication Cores 6 × 32-bit Cortex^®‑R52+ cores (4 of them with checker cores, and 2 in split-lock configuration): Configurable as either 6 cores (4 of them in lockstep configuration) or 5 cores (all of them in lockstep configuration) Arm^® v8-R compliant Single precision floating-point unit (FPU) New privilege level for real-time virtualization 2 cores with Neon™ extensions (for example SIMD, dual precision FPU) 2 Cortex^®‑M4 multipurpose accelerators, both in lockstep configuration 4 eDMA engines in lockstep configuration Memories Up to 20.5 MB on-chip nonvolatile memory (NVM): PCM (phase-change memory) as nonvolatile memory 19.5 MB code NVM, with embedded memory replication for OTA (over-the-air) reprogramming with up to 2× 19.5 MB 1024 KB HSM-dedicated code NVM 640 KB data NVM (512 KB + 128 KB dedicated to HSM) Up to 9280 KB on-chip general-purpose SRAM Security: 2^nd generation hardware security module Cybersecurity: ISO/SAE 21434 compliance (refer to the cybersecurity reference manual for details) On-chip high-performance security module with full support for e-safety vehicle intrusion protected applications (EVITA) Symmetric and asymmetric cryptography processor High-performance lock-stepped AES-light security subsystem for fast ASIL-D cryptographic services Safety: comprehensive new-generation ASIL-D safety concept New state-of-the-art safety measures at all levels of the architecture for most efficient implementation of ISO 26262 ASIL-D functionalities Complete hardware virtualization architecture built on Cortex^®‑R52+ new privilege mode (best-in-class software isolation, real-time support for multiple virtual machines/applications) Device standby/low-power modes Versatile low-power modes Ultra-low power: standby mode for lowest quiescent current with optimized active subsystem (for example standby RAM) and wake-up capability Smart low-power: smart power mode with Cortex^®‑M4 subsystem, extended communications interfaces, and ADC peripheral Peripheral, I/O, and communication interfaces 28 LINFlexD modules 2 dual-channel FlexRay controllers 10 queued serial peripheral interface (SPIQ) modules 2 DSPI with shifted PWM serialization support for lighting applications 2 I²C interfaces 2 SENT modules (15 channels each) 2 PSI5 modules (2 channels each) Enhanced analog-to-digital converter system with: 8 separate 12-bit SAR analog converters (including one supervisor/safety ADC). One 9-bit SAR analog converter for device standby/low-power mode Interconnection with GTM timer for autonomous ADC/GTM subsystem operation Advanced timed I/O capability: Generic timer module (GTM4154) Communication interfaces: Two 10/100/1000 Mbit/s Ethernet controllers compliant with IEEE 802.3-2008: IPv4 and IPv6 checksum modules, AVB, VLAN, and EMC optimized SGMII 19 modular controller area network (MCAN) modules, and 1 time-triggered controller area network (M_TTCAN), all supporting flexible data rate (ISO CAN FD^®) External memory interfaces 2 octo-SPI IPs to support HyperBus™ memory (flash/RAM) devices 1 SDMMC interface

Out of Stock

Quantity	$ per unit	Savings
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Parameters

Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	105.0
Core	Arm Cortex-R52+
ECCN US	5A991.b.4.a
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Automotive Safety Cybersecurity
Package Name	FPBGA 21.3X21.3X1.8 476 P.8 B.55

Description

Key features

Key features
AEC-Q100 SR6 integration MCUs: Have superior real-time and safe performance (with highest ASIL-D capability) Bring hardware-based virtualization technology to MCUs for simplified multiple software integrations at optimized performance Have built-in fast and cost-effective OTA reprogramming capability (with built-in dual-image storage) Offer high-speed security cryptographic services, for example for network authentication Cores 6 × 32-bit Cortex^®‑R52+ cores (4 of them with checker cores, and 2 in split-lock configuration): Configurable as either 6 cores (4 of them in lockstep configuration) or 5 cores (all of them in lockstep configuration) Arm^® v8-R compliant Single precision floating-point unit (FPU) New privilege level for real-time virtualization 2 cores with Neon™ extensions (for example SIMD, dual precision FPU) 2 Cortex^®‑M4 multipurpose accelerators, both in lockstep configuration 4 eDMA engines in lockstep configuration Memories Up to 20.5 MB on-chip nonvolatile memory (NVM): PCM (phase-change memory) as nonvolatile memory 19.5 MB code NVM, with embedded memory replication for OTA (over-the-air) reprogramming with up to 2× 19.5 MB 1024 KB HSM-dedicated code NVM 640 KB data NVM (512 KB + 128 KB dedicated to HSM) Up to 9280 KB on-chip general-purpose SRAM Security: 2^nd generation hardware security module Cybersecurity: ISO/SAE 21434 compliance (refer to the cybersecurity reference manual for details) On-chip high-performance security module with full support for e-safety vehicle intrusion protected applications (EVITA) Symmetric and asymmetric cryptography processor High-performance lock-stepped AES-light security subsystem for fast ASIL-D cryptographic services Safety: comprehensive new-generation ASIL-D safety concept New state-of-the-art safety measures at all levels of the architecture for most efficient implementation of ISO 26262 ASIL-D functionalities Complete hardware virtualization architecture built on Cortex^®‑R52+ new privilege mode (best-in-class software isolation, real-time support for multiple virtual machines/applications) Device standby/low-power modes Versatile low-power modes Ultra-low power: standby mode for lowest quiescent current with optimized active subsystem (for example standby RAM) and wake-up capability Smart low-power: smart power mode with Cortex^®‑M4 subsystem, extended communications interfaces, and ADC peripheral Peripheral, I/O, and communication interfaces 28 LINFlexD modules 2 dual-channel FlexRay controllers 10 queued serial peripheral interface (SPIQ) modules 2 DSPI with shifted PWM serialization support for lighting applications 2 I²C interfaces 2 SENT modules (15 channels each) 2 PSI5 modules (2 channels each) Enhanced analog-to-digital converter system with: 8 separate 12-bit SAR analog converters (including one supervisor/safety ADC). One 9-bit SAR analog converter for device standby/low-power mode Interconnection with GTM timer for autonomous ADC/GTM subsystem operation Advanced timed I/O capability: Generic timer module (GTM4154) Communication interfaces: Two 10/100/1000 Mbit/s Ethernet controllers compliant with IEEE 802.3-2008: IPv4 and IPv6 checksum modules, AVB, VLAN, and EMC optimized SGMII 19 modular controller area network (MCAN) modules, and 1 time-triggered controller area network (M_TTCAN), all supporting flexible data rate (ISO CAN FD^®) External memory interfaces 2 octo-SPI IPs to support HyperBus™ memory (flash/RAM) devices 1 SDMMC interface