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The STCMB1 device embodies a transition mode (TM) PFC, a high voltage double-ended controller for LLC resonant half-bridge, an 800 V-rated high voltage section and the glue logic that supervises the operation of these three blocks.
The PFC section uses a proprietary constant on-time control methodology that does not require a sinusoidal input reference, thereby reducing the system cost and external component count.
It includes also a complete set of protections: a cycle-by-cycle overcurrent (OCP), an output overvoltage (OVP), a feedback failure (FFP, latch-mode), an ac brown-out, boost inductor saturation and inrush current detection both at the start-up and after mains sags or missing cycles.
The half-bridge (HB) section provides two complementary outputs that drive the high-side and low-side MOSFET 180° out-of-phase. The deadtime inserted between the turn-off of an either switch and the turn-on of the other is automatically adjusted to ensure zero voltage switching and higher efficiency from low to full load.
A proprietary control method, timeshift control - TSC, improves dynamic behavior and input ripple rejection resulting in a cleaner output voltage.
At the light-load the IC can be forced to enter a controlled burst mode operation where both the HB and the PFC work intermittently synchronized one to another. This helps to reduce the average switching frequency, thus keeping converter input consumption as low as possible.
At the start-up, in addition to the traditional soft-start based on the frequency-shift, a proprietary hard switching prevention (HSP) function controls the half-bridge to prevent hard switching in the initial cycles. Additionally, the HSP function prevents the converter from working in or too close to the capacitive mode to ensure soft-switching.
The HB is provided with a two-level OCP. The first level is with the frequency shift and delayed shutdown with an automatic restart. A fast shutdown with an automatic restart occurs if this first-level protection cannot limit the primary current. Finally, the device embeds the logic circuitry to coordinate the operation of the PFC, HB and HV start-up generator; in particular: the power-on/off sequencing, X-capacitor discharge, fault handling and synchronous burst mode operation. For the application debug purposes it is possible to externally disable one section at a time and have the other section working standalone.
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