STM32H750VBT6TR

STM32H750VBT6TR

STM32H750VBT6

Active

High-performance and DSP with DP-FPU, Arm Cortex-M7 MCU with 128 Kbytes of Flash memory, 1MB RAM, 480 MHz CPU, L1 cache, external memory interface, JPEG codec, HW crypto, large set of peripherals

Quantity $ per Unit Savings
1 - 9$13.110%
10 - 24$11.8610%
25 - 80$11.3114%
Contact Sales
Out of stock
$13.11
Parameter NameParameter Value
Supply Voltage Min Volt1.71
Supply Voltage Max Volt3.6
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius85.0
CoreArm Cortex-M7
ECCN US5A992.c
ECCN EU5A002.a.4
Packing TypeTray
RoHs compliantEcopack2
GradeIndustrial
Package NameLQFP 100 14x14x1.4 mm

STM32H750xB devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 480 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H750xB devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.


STM32H750xB devices incorporate high-speed embedded memories with a Flash memory of 128 Kbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access.


All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number generator (RNG), and a cryptographic acceleration cell. The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces.

Key features
  • Core
    • 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
  • Memories
    • 128 Kbytes of Flash memory
    • 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain
    • Dual mode Quad-SPI memory interface running up to 133 MHz
    • Flexible external memory controller with up to 32-bit data bus:
      • SRAM, PSRAM, NOR Flash memory clocked up to 133 MHz in synchronous mode

      • SDRAM/LPSDR SDRAM

      • 8/16-bit NAND Flash memories

    • CRC calculation unit
  • Security
    • ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access mode
  • General-purpose input/outputs
    • Up to 168 I/O ports with interrupt capability
  • Reset and power management
    • 3 separate power domains which can be independently clock-gated or switched off:
      • D1: high-performance capabilities

      • D2: communication peripherals and timers

      • D3: reset/clock control/power management

    • 1.62 to 3.6 V application supply and I/Os
    • POR, PDR, PVD and BOR
    • Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
    • Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
    • Voltage scaling in Run and Stop mode (6 configurable ranges)
    • Backup regulator (~0.9 V)
    • Voltage reference for analog peripheral/VREF+