STM32H7A3LGH6Q

High-performance and DSP with DP-FPU, Arm Cortex-M7 MCU with 1MBytes of Flash memory, 1376 KB SRAM, 280 MHz CPU, L1 cache, graphic accelerations, external memory interfaces, SMPS and large set of peripherals

Parameters

Supply Voltage Min Volt	1.62
Supply Voltage Max Volt	3.6
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	85.0
Core	Arm Cortex-M7
ECCN US	3A991.a.2
ECCN EU	NEC
Packing Type	Tray
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	TFBGA 225 13x13x1.2 P 0.8 mm

Description

STM32H7A3xI/G devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 280 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data...
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Key features

Key features
Core 32-bit Arm^® Cortex^®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache allowing to fill one cache line in a single access from the 128-bit embedded Flash memory; frequency up to 280 MHz, MPU, 599 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions Memories Up to 2 Mbytes of Flash memory with read while write support, plus 1 Kbyte of OTP ~1.4 Mbytes of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 1.18 Mbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain 2x Octo-SPI memory interfaces with on-the-fly decryption, I/O multiplexing and support for serial PSRAM/NOR, Hyper RAM/Flash frame formats, running up to 140 MHz in SRD mode and up to 110 MHz in DTR mode Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, NOR Flash memory clocked up to 125 MHz in Synchronous mode SDRAM/LPSDR SDRAM, 8/16-bit NAND Flash memory CRC calculation unit Security ROP, PC-ROP, active tamper, secure firmware upgrade support General-purpose input/outputs Up to 168 I/O ports with interrupt capability Fast I/Os capable of up to 133 MHz Up to 164 5 V-tolerant I/Os Low-power consumption Stop: down to 32 µA with full RAM retention Standby: 2.8 µA (Backup SRAM OFF, RTC/LSE ON, PDR OFF) V_BAT: 0.8 µA with RTC and LSE ON Clock management Internal oscillators: 64 MHz HSI, 48 MHz RC, 4 MHz CSI, 32 kHz LSI External oscillators: 4-50 MHz HSE, 32.768 kHz LSE 3× PLL

Out of Stock

Quantity	$ per unit	Savings
1-9	$16.32	0%
10-24	$15.00	8%
25-99	$14.38	12%
100-249	$12.67	22%
250-499	$12.04	26%
500-959	$11.27	31%
960-10000	$10.34	37%
10000 +	Contact sales

$16.32

Parameters

Supply Voltage Min Volt	1.62
Supply Voltage Max Volt	3.6
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	85.0
Core	Arm Cortex-M7
ECCN US	3A991.a.2
ECCN EU	NEC
Packing Type	Tray
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	TFBGA 225 13x13x1.2 P 0.8 mm

Description

Key features

Key features
Core 32-bit Arm^® Cortex^®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache allowing to fill one cache line in a single access from the 128-bit embedded Flash memory; frequency up to 280 MHz, MPU, 599 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions Memories Up to 2 Mbytes of Flash memory with read while write support, plus 1 Kbyte of OTP ~1.4 Mbytes of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 1.18 Mbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain 2x Octo-SPI memory interfaces with on-the-fly decryption, I/O multiplexing and support for serial PSRAM/NOR, Hyper RAM/Flash frame formats, running up to 140 MHz in SRD mode and up to 110 MHz in DTR mode Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, NOR Flash memory clocked up to 125 MHz in Synchronous mode SDRAM/LPSDR SDRAM, 8/16-bit NAND Flash memory CRC calculation unit Security ROP, PC-ROP, active tamper, secure firmware upgrade support General-purpose input/outputs Up to 168 I/O ports with interrupt capability Fast I/Os capable of up to 133 MHz Up to 164 5 V-tolerant I/Os Low-power consumption Stop: down to 32 µA with full RAM retention Standby: 2.8 µA (Backup SRAM OFF, RTC/LSE ON, PDR OFF) V_BAT: 0.8 µA with RTC and LSE ON Clock management Internal oscillators: 64 MHz HSI, 48 MHz RC, 4 MHz CSI, 32 kHz LSI External oscillators: 4-50 MHz HSE, 32.768 kHz LSE 3× PLL