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STM32WB50CGU5

Ultra-low-power dual core Arm Cortex-M4 MCU 64 MHz, Cortex-M0+ 32 MHz with 1 Mbyte of Flash memory, Bluetooth LE 5.4, 802.15.4, Zigbee, Thread, Matter, AES 256

Supply Voltage Min Volt2.0
Supply Voltage Max Volt3.6
Operating Temp Min Celsius-10.0
Operating Temp Max Celsius85.0
Operating Voltage Min Volt2.0
Operating Voltage Max Volt3.6
CoreArm Cortex-M4
ECCN US5A992.c
ECCN EUNEC
Packing TypeTray
RoHs compliantEcopack2
GradeIndustrial
Package NameUFQFPN 48 7x7x0.55 mm

The STM32WB50CG and STM32WB30CE multiprotocol wireless and ultra-low-power device embeds a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification 5.4 or with IEEE 802.15.4-2011. It contains a dedicated Arm® Cortex®-M0+ for performing all the real-time low...
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Key features
  • Include ST state-of-the-art patented technology
  • Radio
    • 2.4 GHz
    • RF transceiver supporting Bluetooth® 5.4 specification or IEEE 802.15.4-2011 PHY and MAC, supporting Thread 1.3 and Zigbee® 3.0
    • RX sensitivity: -96 dBm (Bluetooth® Low Energy at 1 Mbps), -100 dBm (802.15.4)
    • Programmable output power up to +4 dBm with 1 dB steps
    • Integrated balun to reduce BOM
    • Support for 1 Mbps
    • Support GATT caching
    • Support EATT (enhanced ATT)
    • Support advertising extension
    • Dedicated Arm® 32-bit Cortex® M0+ CPU for real-time Radio layer
    • Accurate RSSI to enable power control
    • Suitable for systems requiring compliance with radio frequency regulations ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66
    • Support for external PA
    • Available integrated passive device (IPD) companion chip for optimized matching solution (MLPF-WB-01E3)
  • Ultra-low-power platform
    • 2.0 to 3.6 V power supply
    • – 10 °C to +85 °C temperature range
    • 14 nA shutdown mode
    • 700 nA Standby mode + RTC + 32 KB RAM
    • 2.25 µA Stop mode + RTC + 128 KB RAM
    • Radio: Rx 7.9 mA / Tx at 0 dBm 8.8 mA
  • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, adaptive real-time accelerator (ART™ Accelerator) allowing 0-wait-state execution from flash memory, frequency up to 64 MHz, MPU, 80 DMIPS and DSP instructions
  • Performance benchmark
    • 1.25 DMIPS/MHz (Drystone 2.1)
    • 219.48 CoreMark® (3.43 CoreMark/MHz at 64 MHz)
  • Energy benckmark
    • 303 ULPMark™ CP score
  • Supply and reset management
    • Ultra-safe, low-power BOR (brownout reset) with five selectable thresholds
    • Ultra-low-power POR/PDR
    • Programmable voltage detector (PVD)
    • VBAT mode with RTC and backup registers
  • Clock sources
    • 32 MHz crystal oscillator with integrated trimming capacitors (Radio and CPU clock)
    • 32 kHz crystal oscillator for RTC (LSE)
    • Internal low-power 32 kHz (±5%) RC (LSI1)
    • Internal low-power 32 kHz (stability ±500 ppm) RC (LSI2)
    • Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25% accuracy)
    • High speed internal 16 MHz factory trimmed RC (±1%)
    • 1x PLL for system clock, ADC
  • Memories
    • 1 MB flash memory with sector protection (PCROP) against R/W operations, enabling radio stack and application
    • 128 KB SRAM, including 64 KB with hardware parity check
    • 20x 32-bit backup register
    • Boot loader supporting USART, SPI, I2C interfaces
    • OTA (over the air) Bluetooth® Low Energy and 802.15.4 update
    • 1 Kbyte (128 double words) OTP
  • Rich analog peripherals (down to 2.0 V)
    • 12-bit ADC 2.13 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps
  • System peripherals
    • Inter processor communication controller (IPCC) for communication with Bluetooth® Low Energy and 802.15.4
    • HW semaphores for resources sharing between CPUs
    • 1x DMA controller (7x channels) supporting ADC, SPI, I2C, USART, AES, timers
    • 1x USART (ISO 7816, IrDA, SPI Master, Modbus and Smartcard mode)
    • 1x SPI 32 Mbit/s
    • 1x I2C (SMBus/PMBus®)
    • 1x 16-bit, four channels advanced timer
    • 2x 16-bit, two channels timer
    • 1x 32-bit, four channels timer
    • 2x 16-bit ultra low power timer
    • 1x independent Systick
    • 1x independent watchdog
    • 1x window watchdog
  • Security and ID
    • Secure firmware installation (SFI) for Bluetooth® Low Energy and 802.15.4 SW stack
    • 2x hardware encryption AES maximum 256-bit for the application, the Bluetooth® Low Energy and IEEE802.15.4
    • HW public key authority (PKA)
    • Cryptographic algorithms: RSA, Diffie-Helman, ECC over GF(p)
    • True random number generator (RNG)
    • Sector protection against R/W operation (PCROP)
    • CRC calculation unit
    • Die information: 96-bit unique ID
    • IEEE 64-bit unique ID, possibility to derive 802.15.4 64-bit and Bluetooth® Low Energy 48-bit EUI
  • Up to 30 fast I/Os, 28 of them 5 V-tolerant
  • Development support
    • Serial wire debug (SWD), JTAG for the application processor
    • Application cross trigger
  • ECOPACK2 compliant package
In stock
Quantity $ per unit Savings
1-9$4.470%
10-99$3.7616%
100-249$3.5920%
250-499$3.3924%
500-999$3.1829%
1000-2499$2.8536%
2500-10000$2.8337%
Contact sales
$4.47
$4.47
Supply Voltage Min Volt2.0
Supply Voltage Max Volt3.6
Operating Temp Min Celsius-10.0
Operating Temp Max Celsius85.0
Operating Voltage Min Volt2.0
Operating Voltage Max Volt3.6
CoreArm Cortex-M4
ECCN US5A992.c
ECCN EUNEC
Packing TypeTray
RoHs compliantEcopack2
GradeIndustrial
Package NameUFQFPN 48 7x7x0.55 mm

The STM32WB50CG and STM32WB30CE multiprotocol wireless and ultra-low-power device embeds a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification 5.4 or with IEEE 802.15.4-2011. It contains a dedicated Arm® Cortex®-M0+ for performing all the real-time low...
Read More

Key features
  • Include ST state-of-the-art patented technology
  • Radio
    • 2.4 GHz
    • RF transceiver supporting Bluetooth® 5.4 specification or IEEE 802.15.4-2011 PHY and MAC, supporting Thread 1.3 and Zigbee® 3.0
    • RX sensitivity: -96 dBm (Bluetooth® Low Energy at 1 Mbps), -100 dBm (802.15.4)
    • Programmable output power up to +4 dBm with 1 dB steps
    • Integrated balun to reduce BOM
    • Support for 1 Mbps
    • Support GATT caching
    • Support EATT (enhanced ATT)
    • Support advertising extension
    • Dedicated Arm® 32-bit Cortex® M0+ CPU for real-time Radio layer
    • Accurate RSSI to enable power control
    • Suitable for systems requiring compliance with radio frequency regulations ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66
    • Support for external PA
    • Available integrated passive device (IPD) companion chip for optimized matching solution (MLPF-WB-01E3)
  • Ultra-low-power platform
    • 2.0 to 3.6 V power supply
    • – 10 °C to +85 °C temperature range
    • 14 nA shutdown mode
    • 700 nA Standby mode + RTC + 32 KB RAM
    • 2.25 µA Stop mode + RTC + 128 KB RAM
    • Radio: Rx 7.9 mA / Tx at 0 dBm 8.8 mA
  • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, adaptive real-time accelerator (ART™ Accelerator) allowing 0-wait-state execution from flash memory, frequency up to 64 MHz, MPU, 80 DMIPS and DSP instructions
  • Performance benchmark
    • 1.25 DMIPS/MHz (Drystone 2.1)
    • 219.48 CoreMark® (3.43 CoreMark/MHz at 64 MHz)
  • Energy benckmark
    • 303 ULPMark™ CP score
  • Supply and reset management
    • Ultra-safe, low-power BOR (brownout reset) with five selectable thresholds
    • Ultra-low-power POR/PDR
    • Programmable voltage detector (PVD)
    • VBAT mode with RTC and backup registers
  • Clock sources
    • 32 MHz crystal oscillator with integrated trimming capacitors (Radio and CPU clock)
    • 32 kHz crystal oscillator for RTC (LSE)
    • Internal low-power 32 kHz (±5%) RC (LSI1)
    • Internal low-power 32 kHz (stability ±500 ppm) RC (LSI2)
    • Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25% accuracy)
    • High speed internal 16 MHz factory trimmed RC (±1%)
    • 1x PLL for system clock, ADC
  • Memories
    • 1 MB flash memory with sector protection (PCROP) against R/W operations, enabling radio stack and application
    • 128 KB SRAM, including 64 KB with hardware parity check
    • 20x 32-bit backup register
    • Boot loader supporting USART, SPI, I2C interfaces
    • OTA (over the air) Bluetooth® Low Energy and 802.15.4 update
    • 1 Kbyte (128 double words) OTP
  • Rich analog peripherals (down to 2.0 V)
    • 12-bit ADC 2.13 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps
  • System peripherals
    • Inter processor communication controller (IPCC) for communication with Bluetooth® Low Energy and 802.15.4
    • HW semaphores for resources sharing between CPUs
    • 1x DMA controller (7x channels) supporting ADC, SPI, I2C, USART, AES, timers
    • 1x USART (ISO 7816, IrDA, SPI Master, Modbus and Smartcard mode)
    • 1x SPI 32 Mbit/s
    • 1x I2C (SMBus/PMBus®)
    • 1x 16-bit, four channels advanced timer
    • 2x 16-bit, two channels timer
    • 1x 32-bit, four channels timer
    • 2x 16-bit ultra low power timer
    • 1x independent Systick
    • 1x independent watchdog
    • 1x window watchdog
  • Security and ID
    • Secure firmware installation (SFI) for Bluetooth® Low Energy and 802.15.4 SW stack
    • 2x hardware encryption AES maximum 256-bit for the application, the Bluetooth® Low Energy and IEEE802.15.4
    • HW public key authority (PKA)
    • Cryptographic algorithms: RSA, Diffie-Helman, ECC over GF(p)
    • True random number generator (RNG)
    • Sector protection against R/W operation (PCROP)
    • CRC calculation unit
    • Die information: 96-bit unique ID
    • IEEE 64-bit unique ID, possibility to derive 802.15.4 64-bit and Bluetooth® Low Energy 48-bit EUI
  • Up to 30 fast I/Os, 28 of them 5 V-tolerant
  • Development support
    • Serial wire debug (SWD), JTAG for the application processor
    • Application cross trigger
  • ECOPACK2 compliant package