STM32WL55JCI6TR

Sub-GHz Wireless Microcontrollers. Dual-core Arm Cortex-M4/M0+ @48 MHz with 256 Kbytes of Flash memory, 64 Kbytes of SRAM. LoRa, (G)FSK, (G)MSK, BPSK modulations. AES 256-bit. Multiprotocol System-on-Chip.

Parameters

Supply Voltage Min Volt	1.8
Supply Voltage Max Volt	3.6
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	85.0
Operating Voltage Min Volt	1.8
Operating Voltage Max Volt	3.6
Core	Arm Cortex-M4
ECCN US	5A992.c
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Industrial

Description

The STM32WL55/54xx long-range wireless and ultra-low-power devices embed a powerful and ultra-low-power LPWAN-compliant radio solution, enabling the following modulations: LoRa®, (G)FSK, (G)MSK, and BPSK.The LoRa® modulation is available in STM32WLx5xx only.These devices are designed to be...
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The LoRa^® modulation is available in STM32WLx5xx only.

These devices are designed to be extremely low-power and are based on the high-performance Arm^® Cortex^®-M4 32-bit RISC core operating at a frequency of up to 48 MHz. This core implements a full set of DSP instructions. It is complemented by an Arm^® Cortex^®-M0+ microcontroller. Both cores implement an independent memory protection unit (MPU) that enhances the application security.

The devices embed high-speed memories (256-Kbyte flash memory, 64-Kbyte SRAM), and an extensive range of enhanced I/Os and peripherals.

The devices also embed several protection mechanisms for embedded flash memory and SRAM: readout protection, write protection and proprietary code readout protection.

In addition, the STM32WL55/54xx devices support the following secure services running on Arm^® Cortex-M0+: unique boot entry capable, secure sub-GHz MAC layer, secure firmware update, secure firmware install and storage and management of secure keys.

These devices offer a 12-bit ADC, a 12-bit DAC low-power sample-and-hold, two ultra-low-power comparators associated with a high-accuracy reference voltage generator.

The devices embed a low-power RTC with a 32-bit sub-second wakeup counter, one 16-bit single-channel timer, two 16-bit four-channel timers (supporting motor control), one 32-bit four-channel timer and three 16-bit ultra-low-power timers.

These devices also embed two DMA controllers (7 channels each) allowing any transfer combination between memory (flash memory, SRAM1 and SRAM2) and peripheral, using the DMAMUX1 for flexible DMA channel mapping.

The devices also feature the following standard and advanced communication interfaces: inter-processor communication controller (mailbox) and semaphores for communication between the two Arm^® Cortex^®-M cores, two USARTs (supporting LIN, smartcard, IrDA, modem control and ISO7816), one low-power UART (LPUART), three I2Cs (SMBus/PMBus), two SPIs (up to 16 MHz, one supporting I²S).

The operating temperature/voltage ranges are –40 °C to +105 °C (+85 °C with radio) from a 1.8 V to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications.

The devices integrate a high-efficiency SMPS step-down converter and independent power supplies for ADC, DAC and comparator analog inputs.

A V_BAT dedicated supply allows the LSE 32.768 kHz oscillator, the RTC and the backup registers to be backed up. The devices can maintain these functions even if the main V_DD is not present, through a CR2032-like battery, a supercap or a small rechargeable battery.

Key features

Key features
Includes ST state-of-the-art patented technology Radio Frequency range: 150 MHz to 960 MHz Modulation: LoRa^®, (G)FSK, (G)MSK and BPSK RX sensitivity: –123 dBm for 2-FSK(at 1.2 Kbit/s), –148 dBm for LoRa^® (at 10.4 kHz, spreading factor 12) Transmitter high output power, programmable up to +22 dBm Transmitter low output power, programmable up to +15 dBm Available integrated passive device (IPD) companion chips for optimized matching, filtering and balun, all in one very compact solution covering each package and each main use cases (22 dBm @ 915 MHz, 14 dBm @ 868 MHz, 17 dBm @ 490 MHz) Compliant with the following radio frequency regulations such as ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 Part 15, 24, 90, and the Japanese ARIB STD-T30, T-67, T-108 Compatible with standardized or proprietary protocols such as LoRaWAN^®, Sigfox™, W-MBus and more (fully open wireless system-on-chip) Ultra-low-power platform 1.8 V to 3.6 V power supply –40 °C to +105 °C temperature range Shutdown mode: 31 nA (V_DD= 3 V) Standby (+ RTC) mode:360 nA (V_DD= 3 V) Stop2 (+ RTC) mode: 1.07 µA (V_DD= 3 V) Active-mode MCU: < 72 µA/MHz (CoreMark^®) Active-mode RX: 4.82 mA Active-mode TX: 15 mA at 10 dBm and 87 mA at 20 dBm (LoRa^® 125 kHz) Core 32-bit Arm^® Cortex^®-M4 CPU Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from flash memory, frequency up to 48 MHz, MPU and DSP instructions 1.25 DMIPS/MHz (Dhrystone 2.1) 32-bit Arm^®Cortex^®-M0+ CPU Frequency up to 48 MHz, MPU 0.95 DMIPS/MHz (Dhrystone 2.1) Security and identification Hardware encryption AES 256-bit True random number generator (RNG) Sector protection against read/write operations (PCROP, RDP, WRP) CRC calculation unit Unique device identifier (64-bit UID compliant with IEEE 802-2001 standard) 96-bit unique die identifier Hardware public key accelerator (PKA) Key management services Secure sub-GHz MAC layer Secure firmware update (SFU) Secure firmware install (SFI) Supply and reset management High-efficiency embedded SMPS step-down converter SMPS to LDO smart switch Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds Ultra-low-power POR/PDR Programmable voltage detector (PVD) V_BAT mode with RTC and 20x32-bit backup registers Clock sources 32 MHz crystal oscillator TCXO support: programmable supply voltage 32 kHz oscillator for RTC with calibration High-speed internal 16 MHz factory trimmed RC (± 1 %) Internal low-power 32 kHz RC Internal multi-speed low-power 100 kHz to 48 MHz RC PLL for CPU, ADC and audio clocks Memories 256-Kbyte flash memory 64-Kbyte RAM 20x32-bit backup register Bootloader supporting USART and SPI interfaces OTA (over-the-air) firmware update capable Sector protection against read/write operations Rich analog peripherals (down to 1.62 V) 12-bit ADC 2.5 Msps, up to 16 bits with hardware oversampling, conversion range up to 3.6 V 12-bit DAC, low-power sample-and-hold 2x ultra-low-power comparators System peripherals Mailbox and semaphores for communication between Cortex^®-M4 and Cortex^®-M0+ firmware Controllers 2x DMA controller (7 channels each) supporting ADC, DAC, SPI, I2C, LPUART, USART, AES and timers 2x USART (ISO 7816, IrDA, SPI) 1x LPUART (low-power) 2x SPI 16 Mbit/s (1 over 2 supporting I2S) 3x I2C (SMBus/PMBus^®) 2x 16-bit 1-channel timer 1x 16-bit 4-channel timer (supporting motor control) 1x 32-bit 4-channel timer 3x 16-bit ultra-low-power timer 1x RTC with 32-bit sub-second wakeup counter 1x independent SysTick 1x independent watchdog 1x window watchdog Up to 43 I/Os, most 5 V-tolerant Development support Serial-wire debug (SWD), JTAG Dual CPU cross trigger capabilities All packages ECOPACK2compliant

Out of Stock

Quantity	$ per unit	Savings
1-9	$10.78	0%
10-24	$9.74	10%
25-99	$9.29	14%
100-249	$8.07	25%
250-499	$7.70	29%
500-999	$7.03	35%
1000-10000	$6.13	43%
10000 +	Contact sales

$10.78