M48Z35Y-70PC1

256 Kbit (32 Kbit x 8) ZEROPOWER® SRAM

Parameters

Operating Range	Commercial
Supply Voltage Min Volt	4.5
Supply Voltage Max Volt	5.5
ECCN US	EAR99
ECCN EU	NEC
Packing Type	Tube
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	PDIP 28 .7

Description

The M48Z35/Y ZEROPOWER®RAM is a 32 K x 8, non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery-backed memory solution.The M48Z35/Y is a...
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Key features

Key features
Integrated, ultra low power SRAM, power-fail control circuit, and battery READ cycle time equals WRITE cycle time Automatic power-fail chip deselect and WRITE protection WRITE protect voltages: (V_PFD= power-fail deselect voltage) M48Z35: V_CC= 4.75 to 5.5 V; 4.5 V ≤ V_PFD≤ 4.75 V M48Z35Y: 4.5 to 5.5 V; 4.2 V ≤ V_PFD≤ 4.5 V Self-contained battery in the CAPHAT^™DIP package Packaging includes a 28-lead SOIC and SNAPHAT^®top (to be ordered separately) Pin and function compatible with JEDEC standard 32 K x 8 SRAMs SOIC package provides direct connection for a SNAPHAT^®top which contains the battery RoHS compliant Lead-free second level interconnect

In stock

Quantity	$ per unit	Savings
1-9	$31.30	0%
10-24	$28.79	8%
25-49	$27.70	12%
50-99	$27.19	13%
100-239	$26.61	15%
240-479	$25.77	18%
480-500	$25.28	19%
500 +	Contact sales

$31.30

Parameters

Operating Range	Commercial
Supply Voltage Min Volt	4.5
Supply Voltage Max Volt	5.5
ECCN US	EAR99
ECCN EU	NEC
Packing Type	Tube
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	PDIP 28 .7

Description

Key features

Key features
Integrated, ultra low power SRAM, power-fail control circuit, and battery READ cycle time equals WRITE cycle time Automatic power-fail chip deselect and WRITE protection WRITE protect voltages: (V_PFD= power-fail deselect voltage) M48Z35: V_CC= 4.75 to 5.5 V; 4.5 V ≤ V_PFD≤ 4.75 V M48Z35Y: 4.5 to 5.5 V; 4.2 V ≤ V_PFD≤ 4.5 V Self-contained battery in the CAPHAT^™DIP package Packaging includes a 28-lead SOIC and SNAPHAT^®top (to be ordered separately) Pin and function compatible with JEDEC standard 32 K x 8 SRAMs SOIC package provides direct connection for a SNAPHAT^®top which contains the battery RoHS compliant Lead-free second level interconnect