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8 Bit SIPO Shift Register Latch (3-State)

Quantity $ per Unit Savings
1 - 9$1.240%
10 - 24$1.139%
25 - 99$1.0714%
100 - 249$0.8730%
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Parameter NameParameter Value
Supply Voltage Min Volt2.0
Supply Voltage Max Volt6.0
Operating Temp Min Celsius-40.0
Operating Temp Max Celsius125.0
Packing TypeTape And Reel
RoHs compliantEcopack3
Package NameTSSOP-16L

The M74HC4094 device is a high speed CMOS 8-bit SIPO shift latch register fabricated with silicon gate C2MOS technology. It consists of an 8-bit shift register and an 8-bit latch with 3-state output buffer. Data is shifted serially through the shift register on the positive going transition of the clock input signal. The output of the last stage (QS) can be used to cascade several devices.

Data on the QS output is transferred to a second output (QS’) on the following negative transition of the clock input signal. The data of each stage of the shift register is provided with a latch, which latches data on the negative going transition of the STROBE input signal. When the STROBE input is held high, data propagates through the latch to a 3-state output buffer. This buffer is enabled when OUTPUT ENABLE input is taken high. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

Key features
  • High speed: fMAX= 80 MHz (typ.) at VCC= 6 V
  • Low power dissipation: ICC= 4 μA (max.) at TA= 25 °C
  • High noise immunity: VNIH= VNIL= 28% VCC(min.)
  • Symmetrical output impedance: |IOH| = IOL= 4 mA (min.)
  • Balanced propagation delays: tPLH≅ tPHL
  • Wide operating voltage range: VCC(opr.) = 2 V to 6 V
  • Pin and function compatible with 74 series 4094
  • ESD performance
    • CDM: 1 kV
    • HBM: 2 kV
    • MM: 200 V