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    SPC582B54E1BD00X

    SPC582B54E1BD00X

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    SPC582B54E1CG00X

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    32-bit Power Architecture MCU for Automotive General Purpose Applications - Chorus family
    Learn More about SPC582B54E1CG00X

    Quantity $ per Unit Savings
    1 - 9$11.130%
    10 - 24$10.0610%
    25 - 99$9.6014%
    100 - 249$8.3425%
    250 - 499$7.9628%
    500$7.2635%
    500 + Contact Sales
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    Parameter NameParameter Value
    Supply Voltage Min Volt3.0
    Supply Voltage Max Volt5.5
    Operating Temp Min Celsius-40.0
    Operating Temp Max Celsius105.0
    Coree200z2
    ECCN US5A991.b.4.a
    ECCN EUNEC
    Packing TypeTape And Reel
    ROHS Compliance GradeEcopack2
    GradeAutomotive Safety
    Package NameTQFP 64 10x10x1.0
    Key features
    • AEC-Q100 qualified
    • High performance e200z2 single core
      • 32-bit Power Architecture technology CPU
      • Core frequency as high as 80 MHz
      • Variable Length Encoding (VLE)
      • Floating Point, End-to-End Error Correction
    • 1088 KB (1024 KB code flash + 64 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
    • 96 KB on-chip general-purpose SRAM
    • Multi-channel direct memory access controller (eDMA) with 16 channels
    • 1 interrupt controller (INTC)
    • Comprehensive new generation ASIL-B safety concept
      • ASIL-B of ISO 26262
      • FCCU for collection and reaction to failure notifications
      • Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
      • Cyclic redundancy check (CRC) unit
      • End-to-end Error Correction Code (e2eECC) logic
    • Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC
    • Body cross triggering unit (BCTU)
      • Triggers ADC conversions from any eMIOS channel
      • Triggers ADC conversions from up to 2 dedicated PIT_RTIs
      • 1 event configuration register dedicated to each timer event allows to define the corresponding ADC channel
      • Synchronization with ADC to avoid collision
    • 1 enhanced 12-bit SAR analog-to-digital converters
      • Up to 27 channels
      • enhanced diagnosis feature
    • Communication interfaces
      • 6 LINFlexD modules
      • 4 deserial serial peripheral interface (DSPI) modules
      • 7 MCAN interfaces with advanced shared memory scheme and ISO CAN FD support
    • Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell
    • Nexus Class 3 debug and trace interface
    • Boot assist Flash (BAF) supports factory progr
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