SR1PAAU

The Smart Reset^TMdevices provide a useful feature which ensures that inadvertent short reset push-button closures do not cause system resets. This is done by implementing an extended Smart Reset input delay time (t_SRC), which ensures a safe reset and eliminates the need for a specific dedicated reset button.

This reset configuration provides versatility and allows the application to distinguish between a software generated interrupt and a hard system reset. When the input push-button is connected to the microcontroller interrupt input, and is closed for a short time, the processor can only be interrupted. If the system still does not respond properly, continuing to keep the push-button closed for the extended setup time t_SRCcauses a hard reset of the processor through the reset output.

The SR1 has one Smart Reset input (SR) with preset delayed Smart Reset setup time (t_SRC). The reset output (RST) is asserted after the Smart Reset input is held active for the selected t_SRCdelay time. The RSToutput remains asserted either until the SRinput goes to inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset pulse duration is fixed for t_REC(i.e. factory-programmed). The device fully operates over a broad V_CCrange from 2.0 V to 5.5 V.