STM32C011F4P7TR

Mainstream Arm Cortex-M0+ MCU with 16 Kbytes of Flash memory, 6 Kbytes RAM, 48 MHz CPU, 2x USART, timers, ADC, comm. I/F, 2-3.6V

Parameters

Supply Voltage Min Volt	2.0
Supply Voltage Max Volt	3.6
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	105.0
Core	Arm Cortex-M0+
ECCN US	3A991.a.2
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	TSSOP-20

Description

The STM32C011x4/x6 mainstream microcontrollers are based on high-performance Arm® Cortex®-M0+ 32-bit RISC core operating at up to 48 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains and ready for...
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Key features

Key features
Includes ST state-of-the-art patented technology Core: Arm^® 32-bit Cortex^®-M0+ CPU, frequency up to 48 MHz -40°C to 85°C/105°C/125°C operating temperature Memories Up to 32 Kbytes of flash memory with protection 6 Kbytes of SRAM with hardware parity check CRC calculation unit Reset and power management Voltage range: 2.0 V to 3.6 V Power-on / power-down reset (POR/PDR) Programmable brownout reset (BOR) Low-power modes:Sleep, Stop, Standby, Shutdown Clock management 4 to 48 MHz crystal oscillator 32 kHz crystal oscillator with calibration Internal 48 MHz RC oscillator (±1 %) Internal 32 kHz RC oscillator (±5 %) Up to 18 fast I/Os All mappable on external interrupt vectors All 5 V-tolerant 3-channel DMA controller with flexible mapping 12-bit, 0.4 µs ADC (up to 13 ext. channels) Conversion range: 0 to 3.6 V 8 timers: 16-bit for advanced motor control, four 16-bit general-purpose, two watchdogs, SysTick timer Calendar RTC with alarm Communication interfaces One I²C-bus interface supporting Fast-mode Plus (1 Mbit/s) with extra current sink; supporting SMBus/PMBus™ and wake-up from Stop mode Two USARTs with master/slave synchronous SPI; one supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wake-up feature One SPI (24 Mbit/s) with 4- to 16-bit programmable bitframe, multiplexed with I²S interface; two extra SPIs through USARTs Development support: serial wire debug (SWD) All packages ECOPACK2 compliant

Out of Stock

Quantity	$ per unit	Savings
1-2499	$1.58	0%
2500-4999	$0.47	70%
5000-10000	$0.45	71%
10000 +	Contact sales

$1.58

Parameters

Supply Voltage Min Volt	2.0
Supply Voltage Max Volt	3.6
Operating Temp Min Celsius	-40.0
Operating Temp Max Celsius	105.0
Core	Arm Cortex-M0+
ECCN US	3A991.a.2
ECCN EU	NEC
Packing Type	Tape And Reel
RoHs compliant	Ecopack2
Grade	Industrial
Package Name	TSSOP-20

Description

Key features

Key features
Includes ST state-of-the-art patented technology Core: Arm^® 32-bit Cortex^®-M0+ CPU, frequency up to 48 MHz -40°C to 85°C/105°C/125°C operating temperature Memories Up to 32 Kbytes of flash memory with protection 6 Kbytes of SRAM with hardware parity check CRC calculation unit Reset and power management Voltage range: 2.0 V to 3.6 V Power-on / power-down reset (POR/PDR) Programmable brownout reset (BOR) Low-power modes:Sleep, Stop, Standby, Shutdown Clock management 4 to 48 MHz crystal oscillator 32 kHz crystal oscillator with calibration Internal 48 MHz RC oscillator (±1 %) Internal 32 kHz RC oscillator (±5 %) Up to 18 fast I/Os All mappable on external interrupt vectors All 5 V-tolerant 3-channel DMA controller with flexible mapping 12-bit, 0.4 µs ADC (up to 13 ext. channels) Conversion range: 0 to 3.6 V 8 timers: 16-bit for advanced motor control, four 16-bit general-purpose, two watchdogs, SysTick timer Calendar RTC with alarm Communication interfaces One I²C-bus interface supporting Fast-mode Plus (1 Mbit/s) with extra current sink; supporting SMBus/PMBus™ and wake-up from Stop mode Two USARTs with master/slave synchronous SPI; one supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wake-up feature One SPI (24 Mbit/s) with 4- to 16-bit programmable bitframe, multiplexed with I²S interface; two extra SPIs through USARTs Development support: serial wire debug (SWD) All packages ECOPACK2 compliant